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IEICE Transactions on Electronics

A High-Speed Interface Based on a Josephson Latching Driver for Adiabatic Quantum-Flux-Parametron Logic

Fumihiro China, Naoki Takeuchi, Hideo Suzuki, Yuki Yamanashi, Hirotaka Terai, Nobuyuki Yoshikawa

Published Dec 2, 2021• 3 citations
Publisher

Abstract

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.

DOI
10.1587/transele.2021sep0002

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Scientific Reports•Nov 21, 2025•3 citations
The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.
Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.
Adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic. The advantage of AQFP is that the switching energy can be reduced by lowering operation frequencies or by increasing the quality factors of Josephson junctions, while keeping the energy barrier height much larger than thermal energy. In other words, both low energy dissipation and low bit error rates (BERs) can be achieved. In this paper, we report the first measurement results of the low BERs of AQFP logic. We used a superconductor voltage driver with a stack of dc superconducting-quantum-interference-devices to amplify the logic signals of AQFP gates into mV-range voltage signals for the BER measurement. Our measurement results showed 3.3 dB and 2.6 dB operation margins, in which BERs were less than 10−20, for 1 Gbps and 2 Gbps data rates, respectively. While the observed BERs were very low, the estimated switching energy for the 1-Gbps operation was only 2 zJ or 30kBT, where kB is the Boltzmann's constant and T is the temperature. Unlike conventional non-adiabatic logic, BERs are not directly associated with switching energy in AQFP.
Various superconductor logic families have been proposed to build energy-efficient digital systems. Each logic family has its respective advantages and disadvantages, so in some systems, it is crucial to combine different superconductor logic families. We previously developed adiabatic quantum-flux-parametron (AQFP)/rapid single-flux-quantum (RSFQ) hybrid systems, such as a readout circuit for superconducting photon detectors and a flux-bias circuit for superconducting quantum bits. To facilitate the design of AQFP/RSFQ hybrid systems, here we propose a self-resetting RSFQ-to-AQFP (SR-R2A) interface as a compact signal converter from RSFQ logic into AQFP logic. The SR-R2A interface comprises an RSFQ latch and an AQFP comparator, where the AQFP comparator detects the flux state of the RSFQ latch. A previously proposed RSFQ-to-AQFP (R2A) interface requires single-flux-quantum clock signals to reset the flux state of the RSFQ part in the R2A interface, whereas the SR-R2A interface does not require such signals because the excitation current for the AQFP part also resets the flux state of the RSFQ latch. This feature allows the SR-R2A to be incorporated into AQFP/RSFQ hybrid systems without hardware overhead. We demonstrate an SR-R2A interface chip, fabricated with the AIST 10-kA/cm2Nb high-speed standard process, at 4.2 K in liquid helium. The experimental results indicate reasonably wide operating margins for the excitation currents and bias voltage for the SR-R2A interface.
Adiabatic quantum-flux-parametron (AQFP) circuits are very low-power due to zero static power consumption and adiabatic switching operations. However, compared to other superconducting circuits, such as rapid single-flux-quantum logic, the operation frequency is relatively low and the latency is relatively large. In this work, we propose multi-excitation AQFP (ME-AQFP) circuits for high-speed and low-latency operations. In ME-AQFP, the intrinsic periodicity of the potential energy of a Josephson device with respect to applied magnetic fluxes is utilized to multiply operation frequencies and reduce latency. In a numerical simulation, we demonstrated an ME-AQFP AND gate, which operates at 10 GHz or 20 GHz with 5-GHz excitation currents. We also evaluated the energy efficiency of ME-AQFP circuits. In an experiment, we successfully demonstrated an ME-AQFP XOR gate and an ME-AQFP full adder.
We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than ±30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.