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IEEE Transactions on Applied Superconductivity

Self-Resetting Interface Between Rapid Single-Flux-Quantum and Adiabatic Quantum-Flux-Parametron Circuits

Mikiya Naruse, Nobuyuki Yoshikawa, Naoki Takeuchi

Published Jul 26, 2023• 0 citations
Publisher

Abstract

Various superconductor logic families have been proposed to build energy-efficient digital systems. Each logic family has its respective advantages and disadvantages, so in some systems, it is crucial to combine different superconductor logic families. We previously developed adiabatic quantum-flux-parametron (AQFP)/rapid single-flux-quantum (RSFQ) hybrid systems, such as a readout circuit for superconducting photon detectors and a flux-bias circuit for superconducting quantum bits. To facilitate the design of AQFP/RSFQ hybrid systems, here we propose a self-resetting RSFQ-to-AQFP (SR-R2A) interface as a compact signal converter from RSFQ logic into AQFP logic. The SR-R2A interface comprises an RSFQ latch and an AQFP comparator, where the AQFP comparator detects the flux state of the RSFQ latch. A previously proposed RSFQ-to-AQFP (R2A) interface requires single-flux-quantum clock signals to reset the flux state of the RSFQ part in the R2A interface, whereas the SR-R2A interface does not require such signals because the excitation current for the AQFP part also resets the flux state of the RSFQ latch. This feature allows the SR-R2A to be incorporated into AQFP/RSFQ hybrid systems without hardware overhead. We demonstrate an SR-R2A interface chip, fabricated with the AIST 10-kA/cm2Nb high-speed standard process, at 4.2 K in liquid helium. The experimental results indicate reasonably wide operating margins for the excitation currents and bias voltage for the SR-R2A interface.

DOI
10.1109/tasc.2023.3299153

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Various superconductor logic families have been proposed to build energy-efficient digital systems. Each logic family has its respective advantages and disadvantages, so in some systems, it is crucial to combine different superconductor logic families. We previously developed adiabatic quantum-flux-parametron (AQFP)/rapid single-flux-quantum (RSFQ) hybrid systems, such as a readout circuit for superconducting photon detectors and a flux-bias circuit for superconducting quantum bits. To facilitate the design of AQFP/RSFQ hybrid systems, here we propose a self-resetting RSFQ-to-AQFP (SR-R2A) interface as a compact signal converter from RSFQ logic into AQFP logic. The SR-R2A interface comprises an RSFQ latch and an AQFP comparator, where the AQFP comparator detects the flux state of the RSFQ latch. A previously proposed RSFQ-to-AQFP (R2A) interface requires single-flux-quantum clock signals to reset the flux state of the RSFQ part in the R2A interface, whereas the SR-R2A interface does not require such signals because the excitation current for the AQFP part also resets the flux state of the RSFQ latch. This feature allows the SR-R2A to be incorporated into AQFP/RSFQ hybrid systems without hardware overhead. We demonstrate an SR-R2A interface chip, fabricated with the AIST 10-kA/cm2Nb high-speed standard process, at 4.2 K in liquid helium. The experimental results indicate reasonably wide operating margins for the excitation currents and bias voltage for the SR-R2A interface.
Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.
We investigated interface circuits between rapid single-flux-quantum (RSFQ) circuits and adiabatic quantum-flux-parametron (AQFP) circuits for a high-speed and low-power hybrid computing system. In addition, the interface circuits allow us to use long-distance interconnections based on single-flux-quantum (SFQ) passive transmission lines between AQFP gates. The target frequency of interface circuits is several gigahertz. There are two types of interface circuits. The RSFQ/AQFP interface circuit, which transmits a signal from RSFQ circuits to AQFP gates, was realized by coupling an RSFQ toggle flip-flop (TFF) to an AQFP buffer gate. The simulated bias margins of the RSFQ TFF and the excitation current margin of the RSFQ/AQFP interface were 2.22 mA ± 24.7% and 1.71 mA ± 25.0%, respectively. The AQFP/RSFQ interface circuit, which transmits a signal from AQFP gates to RSFQ circuits, was designed by using a high-sensitive magnetically coupled dc/SFQ converter (MC-dc/SFQ) to detect an output current of an AQFP buffer gate. The simulated bias margins of the MC-dc/SFQ and the excitation current margin of the AQFP/RSFQ interface were 0.558 mA ± 20.5% and 1.95 mA ± 36.1%, respectively. We also fabricated and measured the interface circuits.
In this paper, we designed and demonstrated interface circuits between AQFP (adiabatic quantum-flux-parametron) and RSFQ (rapid single-flux-quantum) circuits according to the established AQFP and RSFQ cell libraries using the MIT LL SFQ5ee process. The principles of these interfaces are based on ones that were previously designed and demonstrated using a four-metal-layer superconductor process. The AQFP-to-RSFQ interface is based on an RSFQ comparator, where an output current from an AQFP buffer is converted to an SFQ pulse output. The RSFQ-to-AQFP interface is based on an RSFQ D flip-flop, where the internal state of the D flip-flop is read out by an AQFP buffer. Thanks to the eight-metal-layer process, the interfaces can be designed with reduced circuit area compared to original designs with the four-metal-layer process. We designed, fabricated, and tested an AQFP-RSFQ hybrid multiplexer test circuit as an example of utilization of the interfaces, which results in correct operation with reasonably wide bias margins in low-frequency tests.
The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.
Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor logic family. AQFP logic gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement an energy-efficient switching process, adiabatic switching. We have proposed a low-latency clocking scheme, delay-line clocking, and demonstrated basic AQFP logic gates. In order to test more complex circuits, a serializer/deserializer (SerDes) should be incorporated into the AQFP circuit under test, since the number of input/output (I/O) cables is limited by equipment. Therefore, in the present study we propose and develop a novel SerDes for testing delay-line-clocked AQFP circuits by combining AQFP and rapid single-flux-quantum (RSFQ) logic families, which we refer to as the AQFP/RSFQ hybrid SerDes. The hybrid SerDes comprises RSFQ shift registers to facilitate the data storage during serial-to-parallel and parallel-to-serial conversion. Furthermore, all the component circuits in the hybrid SerDes are clocked by the identical excitation current to synchronize the AQFP and RSFQ parts. We fabricate and demonstrate a delay-line-clocked AQFP circuit (8-to-3 encoder, which is the largest delay-line-clocked circuit ever designed) integrated with the hybrid SerDes at 4.2 K up to 4.5 GHz. Our measurement results indicate that the hybrid SerDes enables the testing of delay-line-clocked AQFP circuits with only a few I/O cables and is thus a powerful tool for the development of very large-scale integration AQFP circuits.