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IEEE Transactions on Applied Superconductivity

High-Speed Experimental Demonstration of Adiabatic Quantum-Flux-Parametron Gates Using Quantum-Flux-Latches

Naoki Takeuchi, Thomas Ortlepp, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Apr 7, 2014• 9 citations
Publisher

Abstract

We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than ±30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates.

DOI
10.1109/tasc.2014.2311444

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We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than ±30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates.
We propose and discuss quantum-flux-latch (QFL) based circuits for adiabatic quantum-flux-parametron (AQFP) logic. The QFL-based XOR (QXOR) gate is a novel XOR gate. The circuit schematic of the QXOR is the same as that of a QFL, but QXORs operate on a different operation principle due to ac biasing. We designed and fabricated the QXOR and the half adder including a QXOR. We successfully demonstrated correct logic operations of these circuits at 4.2 K in the low-speed function test. Also, we estimated the energy dissipation of the QFL using a circuit simulator. The estimated energy dissipation was $\sim$0.2 aJ/cycle.
We have studied ultra-low-power superconductor circuits using adiabatic quantum flux parametron (AQFP) logic. Latches, which store logic data in logic circuits, are indispensable logic elements in the realization of AQFP computing systems. Among them, feedback latches, which hold data by using a feedback loop, have advantages in terms of their wide operation margins and high stability. Their drawbacks are their large junction counts and long latency. In this paper, we propose a majority gate-based feedback latch for AQFP logic with a reduced number of junctions. We designed and fabricated the proposed AQFP latches using a standard National Institute of Advanced Industrial Science and Technology (AIST) process. The measurement results showed that the feedback latches operate with wide operation margins that are comparable with circuit simulation results.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic stands as an energy-efficient superconductor logic family relying on ac excitations. Though a four-phase clocking scheme has been commonly applied to excite and clock AQFP circuits, the cost of multiple sources and long between-stage latency (a quarter clock cycle) remain unsatisfactory. These drawbacks are more severe for sequential logics, where feedback loops require both down-flow and reverse-flow AQFP gates, necessitating extra buffers and imposing a limit on operating depth at the same time. To overcome these restrictions, in this paper, we introduce a novel mixed clocking scheme for low-latency AQFP logic circuits allowing feedback loops. In particular, the down-flow part of the AQFP circuit is excited by an ac current through delay-lines, which can reduce the latency from input to output stages. Meanwhile, the reverse-flow part is clocked by 2 other ac currents with 90° phase difference to reduce the buffering gates. The proposed clocking scheme is first applied to a fundamental logic circuit, confirming correct functionality and low-latency operations for diverse feedback conditions. For experimental validation, we design and fabricate a 3-bit AQFP counter using the proposed clocking scheme based on an on-chip clock splitter. The circuit is examined at 4 GHz under 4.2 K temperature, where we obtain desired operations and wide excitation margins.
Abstract We have been developing adiabatic quantum-flux-parametron (AQFP) circuits as an ultra-low-power superconductor logic for energy-efficient computing. In a previous study, we proposed and demonstrated a quantum-flux-latch (QFL), which is a compact and compatible latch for AQFP logic. The QFL is composed of an AQFP buffer gate and a storage loop, which are directly connected to each other. However, the operation margins were not sufficiently wide due to a trade-off between the operation margins of the storage loop and that of the buffer gate. In this present study, we propose a magnetically coupled QFL (MC-QFL), where the storage loop and the buffer gate are physically separated and magnetically coupled to each other to eliminate the trade-off in the operation margins. The simulation results showed that the critical parameter margin of the MC-QFL is twice as large as that of the previously designed QFL. For comparison, we fabricated and demonstrated both the previously designed QFL and the newly designed MC-QFL. The measurement results showed that the MC-QFL has wider operation margins compared with the previously designed QFL.
The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1GHz and 4GHz, respectively.
Abstract Adiabatic quantum flux parametron (AQFP) is energy-efficient superconducting logic that operates with zero static energy consumption and extremely small dynamic energy consumption thanks to the adiabatic switching of the logic gates. One drawback in AQFP logic circuits is the wire length and fan-out limitations because of the low driving ability of the logic gates, which results in a large circuit area and significant latency. In the present study, we propose AQFP boosters with high driving ability. Two types of AQFP boosters are proposed: one is composed of a parallel connection of AQFP buffers, and the other uses multistage buffers driven by one excitation clock. We evaluated the maximum wire length of the proposed boosters by circuit simulations, including thermal noises, and found that the maximum wire length is 3.9 mm for fan-out one and 1 mm for fan-out four. We implemented the boosters and demonstrated their correct operations at low-speed tests. We also demonstrated a 5-to-31 decoder using the proposed boosters. It was shown that the circuit area, latency, and energy consumption were improved by about 30% compared to the design without the boosters.