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IEEE Transactions on Applied Superconductivity

Experimental demonstration of quantum-flux-latch-based circuits

Naoki Takeuchi, Thomas Ortlepp, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Jan 1, 2014• 2 citations
Publisher

Abstract

We propose and discuss quantum-flux-latch (QFL) based circuits for adiabatic quantum-flux-parametron (AQFP) logic. The QFL-based XOR (QXOR) gate is a novel XOR gate. The circuit schematic of the QXOR is the same as that of a QFL, but QXORs operate on a different operation principle due to ac biasing. We designed and fabricated the QXOR and the half adder including a QXOR. We successfully demonstrated correct logic operations of these circuits at 4.2 K in the low-speed function test. Also, we estimated the energy dissipation of the QFL using a circuit simulator. The estimated energy dissipation was $\sim$0.2 aJ/cycle.

DOI
10.1109/tasc.2014.2374472

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We propose and discuss quantum-flux-latch (QFL) based circuits for adiabatic quantum-flux-parametron (AQFP) logic. The QFL-based XOR (QXOR) gate is a novel XOR gate. The circuit schematic of the QXOR is the same as that of a QFL, but QXORs operate on a different operation principle due to ac biasing. We designed and fabricated the QXOR and the half adder including a QXOR. We successfully demonstrated correct logic operations of these circuits at 4.2 K in the low-speed function test. Also, we estimated the energy dissipation of the QFL using a circuit simulator. The estimated energy dissipation was ∼\sim∼0.2 aJ/cycle.
We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than ±30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates.
We have been investigating an ultra-low-power adiabatic quantum-flux-parametron (AQFP) logic, the energy dissipation of which can be decreased by changing its potential energy slowly or adiabatically. In the present study, we designed basic AQFP logic gates and an AQFP 1-bit full adder, and examined their operations through simulations and experiments. The AQFP 1-bit full adder is composed of 46 Josephson junctions, which is approximately one-quarter the number of junctions of a full adder using conventional rapid single-flux-quantum logic. The measurement results indicated that the AQFP 1-bit full adder has a wide current bias margin of as large as ±27.8%.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The latency of AQFP circuits is relatively long compared to that of other superconductor logic families and thus such circuits require low-latency clocking schemes. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current, and demonstrated a simple AQFP buffer chain that adopts delay-line clocking. However, it is unclear whether more complex AQFP circuits can adopt delay-line clocking. In the present study, we demonstrate AQFP logic gates (AND and XOR gates) that use delay-line clocking as a step towards implementing large-scale AQFP circuits with delay-line clocking. AND and XOR gates with a latency of approximately 20 ps per gate are shown to operate at up to 5 and 4 GHz, respectively, in experiments. We also demonstrate that delay-line clocking enables phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. The results indicate that delay-line clocking can enable low-latency, low-energy, large-scale AQFP circuits.
Abstract We have been developing adiabatic quantum-flux-parametron (AQFP) circuits as an ultra-low-power superconductor logic for energy-efficient computing. In a previous study, we proposed and demonstrated a quantum-flux-latch (QFL), which is a compact and compatible latch for AQFP logic. The QFL is composed of an AQFP buffer gate and a storage loop, which are directly connected to each other. However, the operation margins were not sufficiently wide due to a trade-off between the operation margins of the storage loop and that of the buffer gate. In this present study, we propose a magnetically coupled QFL (MC-QFL), where the storage loop and the buffer gate are physically separated and magnetically coupled to each other to eliminate the trade-off in the operation margins. The simulation results showed that the critical parameter margin of the MC-QFL is twice as large as that of the previously designed QFL. For comparison, we fabricated and demonstrated both the previously designed QFL and the newly designed MC-QFL. The measurement results showed that the MC-QFL has wider operation margins compared with the previously designed QFL.
Adiabatic quantum flux parametron (AQFP) is a very energy-efficient superconductor logic. In AQFP logic, dynamic energy dissipation can be drastically reduced due to adiabatic switching operations using ac excitation currents. In the present study, we evaluated circuit yields using a large-scale AQFP circuit composed of as many as 10,000 AQFP gates with approximately 20,000 Josephson junctions. We measured eleven chips from four wafers and obtained circuit yields of 48% for 1,000-gate circuits and 22% for 10,000-gate circuits, respectively. In all the circuits, which worked correctly, the margins of excitation currents were as wide as approximately ±20%.
Adiabatic quantum-flux-parametron (AQFP) circuits are very low-power due to zero static power consumption and adiabatic switching operations. However, compared to other superconducting circuits, such as rapid single-flux-quantum logic, the operation frequency is relatively low and the latency is relatively large. In this work, we propose multi-excitation AQFP (ME-AQFP) circuits for high-speed and low-latency operations. In ME-AQFP, the intrinsic periodicity of the potential energy of a Josephson device with respect to applied magnetic fluxes is utilized to multiply operation frequencies and reduce latency. In a numerical simulation, we demonstrated an ME-AQFP AND gate, which operates at 10 GHz or 20 GHz with 5-GHz excitation currents. We also evaluated the energy efficiency of ME-AQFP circuits. In an experiment, we successfully demonstrated an ME-AQFP XOR gate and an ME-AQFP full adder.