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IEEE Transactions on Applied Superconductivity

Simulation and Experimental Demonstration of Logic Circuits Using an Ultra-Low-Power Adiabatic Quantum-Flux-Parametron

Koji Inoue, Naoki Takeuchi, Kei Ehara, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Dec 24, 2012• 39 citations
Publisher

Abstract

We have been investigating an ultra-low-power adiabatic quantum-flux-parametron (AQFP) logic, the energy dissipation of which can be decreased by changing its potential energy slowly or adiabatically. In the present study, we designed basic AQFP logic gates and an AQFP 1-bit full adder, and examined their operations through simulations and experiments. The AQFP 1-bit full adder is composed of 46 Josephson junctions, which is approximately one-quarter the number of junctions of a full adder using conventional rapid single-flux-quantum logic. The measurement results indicated that the AQFP 1-bit full adder has a wide current bias margin of as large as ±27.8%.

DOI
10.1109/tasc.2012.2236133

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We have been investigating an ultra-low-power adiabatic quantum-flux-parametron (AQFP) logic, the energy dissipation of which can be decreased by changing its potential energy slowly or adiabatically. In the present study, we designed basic AQFP logic gates and an AQFP 1-bit full adder, and examined their operations through simulations and experiments. The AQFP 1-bit full adder is composed of 46 Josephson junctions, which is approximately one-quarter the number of junctions of a full adder using conventional rapid single-flux-quantum logic. The measurement results indicated that the AQFP 1-bit full adder has a wide current bias margin of as large as ±27.8%.
Adiabatic quantum flux parametron (AQFP) is a very energy-efficient superconductor logic. In AQFP logic, dynamic energy dissipation can be drastically reduced due to adiabatic switching operations using ac excitation currents. In the present study, we evaluated circuit yields using a large-scale AQFP circuit composed of as many as 10,000 AQFP gates with approximately 20,000 Josephson junctions. We measured eleven chips from four wafers and obtained circuit yields of 48% for 1,000-gate circuits and 22% for 10,000-gate circuits, respectively. In all the circuits, which worked correctly, the margins of excitation currents were as wide as approximately ±20%.
We optimized the circuit parameters of a low-power adiabatic quantum-flux-parametron (AQFP) gate in terms of both bit energy and bias margin and confirmed that the bit energy of the optimized gate with a rise time of 200 ps can be decreased to 6% ofIcΦ0, whereIcis the critical current of the Josephson junctions and Φ0is the single flux quantum. In addition, we investigated the effect of thermal noise on the operation of the optimized AQFP gate. The bias margins and bit error rate of the AQFP gate were examined at finite temperature through circuit simulations, in which the thermal noise was taken into account using the Monte Carlo method. The bias margin of the AQFP gate with bias margins of ±26% at zero temperature shrunk to ±19.4% at 4.2 K, but is still large enough for circuit applications.
We have been developing the adiabatic quantum-flux-parametron (AQFP), which is an ultra-low-power superconductor logic family. To date, somewhat large AQFP circuits, such as a 4-bit microprocessor and an 8-bit adder, have been demonstrated. To design much larger devices, space-efficient logic circuits are needed. Therefore, in a previous study, we proposed the directly coupled quantum-flux-parametron (DQFP). DQFP circuits propagate data via a direct connection, whereas AQFP circuits propagate data via transformers, which can occupy a large part of the gate area. Thus, DQFP circuits are more space-efficient than AQFP circuits. In this study, we optimized the circuit parameters for DQFP logic cells using numerical simulations from the viewpoint of excitation current margins, component parameter margins, and energy dissipation. We also designed the physical layout of the optimized DQFP cells, fabricated chips, and demonstrated basic DQFP circuits with the optimized cells.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells.
Adiabatic quantum-flux-parametron (AQFP) logic can achieve high energy-efficiency. The bit energy and bit-error-rate (BER) of AQFP gates with under-damped Josephson junctions were simulated. The results indicate that the bit energy reaches 12 yJ, which is only 20% of the thermal energy at 4.2 K, using unshunted 50-μA junctions and excitation currents with a rise/fall time of 2000 ps. Although the bit energy is extremely small, the bias margin, where the BER is less than 10−23, is approximately ±22%. These results indicate there is no minimum energy limitation for the operation of AQFP gates unless the entropy of the system decreases.
Ultra-low-power adiabatic quantum flux parametron (QFP) logic is investigated since it has the potential to reduce the bit energy per operation to the order of the thermal energy. In this approach, nonhysteretic QFPs are operated slowly to prevent nonadiabatic energy dissipation occurring during switching events. The designed adiabatic QFP gate is estimated to have a dynamic energy dissipation of 12% of I c Φ 0 for a rise/fall time of 1000 ps. It can be further reduced by reducing circuit inductances. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their correct operation was confirmed.