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Superconductor Science and Technology

Magnetically coupled quantum-flux-latch with wide operation margins

Naoki Tsuji, Naoki Takeuchi, Tatsuya Narama, Thomas Ortlepp, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Sep 29, 2015• 4 citations
Publisher

Abstract

Abstract We have been developing adiabatic quantum-flux-parametron (AQFP) circuits as an ultra-low-power superconductor logic for energy-efficient computing. In a previous study, we proposed and demonstrated a quantum-flux-latch (QFL), which is a compact and compatible latch for AQFP logic. The QFL is composed of an AQFP buffer gate and a storage loop, which are directly connected to each other. However, the operation margins were not sufficiently wide due to a trade-off between the operation margins of the storage loop and that of the buffer gate. In this present study, we propose a magnetically coupled QFL (MC-QFL), where the storage loop and the buffer gate are physically separated and magnetically coupled to each other to eliminate the trade-off in the operation margins. The simulation results showed that the critical parameter margin of the MC-QFL is twice as large as that of the previously designed QFL. For comparison, we fabricated and demonstrated both the previously designed QFL and the newly designed MC-QFL. The measurement results showed that the MC-QFL has wider operation margins compared with the previously designed QFL.

DOI
10.1088/0953-2048/28/11/115013

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Abstract We have been developing adiabatic quantum-flux-parametron (AQFP) circuits as an ultra-low-power superconductor logic for energy-efficient computing. In a previous study, we proposed and demonstrated a quantum-flux-latch (QFL), which is a compact and compatible latch for AQFP logic. The QFL is composed of an AQFP buffer gate and a storage loop, which are directly connected to each other. However, the operation margins were not sufficiently wide due to a trade-off between the operation margins of the storage loop and that of the buffer gate. In this present study, we propose a magnetically coupled QFL (MC-QFL), where the storage loop and the buffer gate are physically separated and magnetically coupled to each other to eliminate the trade-off in the operation margins. The simulation results showed that the critical parameter margin of the MC-QFL is twice as large as that of the previously designed QFL. For comparison, we fabricated and demonstrated both the previously designed QFL and the newly designed MC-QFL. The measurement results showed that the MC-QFL has wider operation margins compared with the previously designed QFL.
We have studied ultra-low-power superconductor circuits using adiabatic quantum flux parametron (AQFP) logic. Latches, which store logic data in logic circuits, are indispensable logic elements in the realization of AQFP computing systems. Among them, feedback latches, which hold data by using a feedback loop, have advantages in terms of their wide operation margins and high stability. Their drawbacks are their large junction counts and long latency. In this paper, we propose a majority gate-based feedback latch for AQFP logic with a reduced number of junctions. We designed and fabricated the proposed AQFP latches using a standard National Institute of Advanced Industrial Science and Technology (AIST) process. The measurement results showed that the feedback latches operate with wide operation margins that are comparable with circuit simulation results.
We have been developing the adiabatic quantum-flux-parametron (AQFP), which is an ultra-low-power superconductor logic family. To date, somewhat large AQFP circuits, such as a 4-bit microprocessor and an 8-bit adder, have been demonstrated. To design much larger devices, space-efficient logic circuits are needed. Therefore, in a previous study, we proposed the directly coupled quantum-flux-parametron (DQFP). DQFP circuits propagate data via a direct connection, whereas AQFP circuits propagate data via transformers, which can occupy a large part of the gate area. Thus, DQFP circuits are more space-efficient than AQFP circuits. In this study, we optimized the circuit parameters for DQFP logic cells using numerical simulations from the viewpoint of excitation current margins, component parameter margins, and energy dissipation. We also designed the physical layout of the optimized DQFP cells, fabricated chips, and demonstrated basic DQFP circuits with the optimized cells.
We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than ±30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates.
We propose and discuss quantum-flux-latch (QFL) based circuits for adiabatic quantum-flux-parametron (AQFP) logic. The QFL-based XOR (QXOR) gate is a novel XOR gate. The circuit schematic of the QXOR is the same as that of a QFL, but QXORs operate on a different operation principle due to ac biasing. We designed and fabricated the QXOR and the half adder including a QXOR. We successfully demonstrated correct logic operations of these circuits at 4.2 K in the low-speed function test. Also, we estimated the energy dissipation of the QFL using a circuit simulator. The estimated energy dissipation was $\sim$0.2 aJ/cycle.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells.
Abstract Adiabatic quantum-flux-parametron (AQFP) logic is one of the most promising superconductor logic families as a candidate to achieve future energy-efficient high-performance information processing systems. The static power of AQFP logic is zero because of ac flux bias, and the switching energy is ∼zJ at 5 GHz due to adiabatic switching. In this study, we propose a design method using offset buffers to reduce the dimension of AQFP circuits; in particular, we focus on the reduction in the horizontal dimension (which is parallel to excitation current) because in AQFP circuits the horizontal dimension tends to be greater than the vertical dimension (which is perpendicular to excitation current). Offset buffers are buffers with offset input signals. The use of offset buffers enables us to eliminate constant cells (which generate constant 0 s and 1 s) from some logic gates, so that the horizontal dimension of logic gates such as AND and OR gates can be significantly reduced. We designed AND and OR gates with offset buffers, and demonstrated them with wide operating margins. Then, we designed and demonstrated a 4–16 decoder using the AND gate with an offset buffer. We found that the horizontal dimension and area of a 4–16 decoder can be reduced by 33% and 26%, respectively, via the use of offset buffers.