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IEEE Transactions on Applied Superconductivity

Film Stress Influence on Nb/Al-AlO x /Nb Josephson Junctions

Yu Wu, Liliang Ying, Guanqun Li, Xue Zhang, Wei Peng, Jie Ren, Zhen Wang

Published Mar 18, 2019• 26 citations
Publisher

Abstract

Nb/Al-AlOx/Nb Josephson junctions are widely used in superconducting quantum interference devices and rapid single flux quantum (RSFQ) circuits. Very large-scale RSFQ integration often has a strict requirement on wafer-scale junction qualities. In particular, Nb film stress in Nb/Al-AlOx/Nb trilayer based Josephson junctions is a critical factor affecting their qualities. In this work, we develop a multi-step sputtering process to prepare Nb films with different combinations of stress and roughness to investigate the correlation between Nb film stress and junction quality. In particular, this method allows us to prepare Nb films with almost the same roughness but different stress, a key factor to study solely the influence of stress on junction qualities. Our measurements indicate that within a very tight range of film roughness (less than 2 nm), tensile film stress is found to decrease the quality of Nb/Al-AlOx/Nb Josephson junctions and larger film roughness has a positive effect on junction quality. By decreasing the total tensile stress and increasing the film roughness properly, we fabricated Nb/Al-AlOx/Nb Josephson junctions with a high quality factor characterized by Rsg/RN(30 on average). The minimum size of junctions was 1 μm.

DOI
10.1109/tasc.2019.2904589

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Nb/Al-AlOx/Nb Josephson junctions are widely used in superconducting quantum interference devices and rapid single flux quantum (RSFQ) circuits. Very large-scale RSFQ integration often has a strict requirement on wafer-scale junction qualities. In particular, Nb film stress in Nb/Al-AlOx/Nb trilayer based Josephson junctions is a critical factor affecting their qualities. In this work, we develop a multi-step sputtering process to prepare Nb films with different combinations of stress and roughness to investigate the correlation between Nb film stress and junction quality. In particular, this method allows us to prepare Nb films with almost the same roughness but different stress, a key factor to study solely the influence of stress on junction qualities. Our measurements indicate that within a very tight range of film roughness (less than 2 nm), tensile film stress is found to decrease the quality of Nb/Al-AlOx/Nb Josephson junctions and larger film roughness has a positive effect on junction quality. By decreasing the total tensile stress and increasing the film roughness properly, we fabricated Nb/Al-AlOx/Nb Josephson junctions with a high quality factor characterized by Rsg/RN(30 on average). The minimum size of junctions was 1 μm.
The Nb/Al-AlOx/Nb Josephson junction serves as the core component of mainstream low-temperature superconducting devices. With the growing demand for scaling up superconducting circuits, increasing the process temperature has become a key technical direction. However, during higher-temperature processing, the difference in the coefficient of thermal expansion between niobium and the substrate introduces significant thermal stress, which degrades junction quality. To mitigate the adverse effects of thermal stress, this paper proposes a stress pre-compensation method: by pre-tuning the residual stress of the bottom niobium electrode, the thermal stress generated in subsequent high-temperature steps is counteracted, thereby maintaining the total stress in the bottom electrode at a low level. In experiments, a series of Josephson junctions with different bottom-electrode stresses were electrically characterized at 4.2 K before and after annealing. The results show that controlling the residual stress of the bottom electrode within a specific tensile range can improve the post-annealing yield. After annealing at 250 ℃ for 30 min, junctions with an initially tensile-stressed bottom Nb electrode exhibited approximately a 14% higher yield compared to those with compressive stress. This trend was also verified in the annealing process of Nb/Al-AlOx-Al*/Nb Josephson junctions.
A trilayer deposition process for making high quality all-refractory Nb/AlOx/Nb Josephson junctions is described. The sputtering parameters were optimized to deposit very uniform Al films, less than 5 nm in thickness. We found that it was essential to keep the substrate temperature below 40 °C during Al deposition but not during Nb depositions. Rapid anodization of the Nb counterelectrode allowed us to use positive photoresist as an anodization mask even for submicron geometries. The dc superconducting quantum interference devices made with this process have the lowest intrinsic energy sensitivity reported to date for an all-refractory technology.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.
Abstract Josephson tunnel junctions form the basis for various superconductor electronic devices. For this reason, enormous efforts are routinely taken to establish and later on maintain a scalable and reproducible wafer-scale manufacturing process for high-quality Josephson junctions. Here, we present an anodization-free fabrication process for Nb/Al-AlO x /Nb cross-type Josephson junctions that requires only a small number of process steps and that is in general intrinsically compatible with wafer-scale fabrication. We show that the fabricated junctions are of very high quality and, compared to other junction types, exhibit not only a significantly reduced capacitance but also an almost rectangular critical current density profile. Our process hence enables the usage of low capacitance Josephson junctions for superconductor electronic devices such as ultra-low noise dc-superconducting quantum interference devices (SQUIDs), microwave SQUID multiplexers based on non-hysteretic rf-SQUIDs and RFSQ circuits.
Superconducting qubits stand as a pivotal platform for quantum computing, where scalable fabrication is crucial for building complex quantum circuits. Here, we develop a fabrication process for Nb/Al-AlOx/Nb tri-layer Josephson junctions on 4-inch silicon wafers using full-stepper lithography. Utilizing this process, we have produced both transmon and C-shunt flux qubits. The well-behavedI-Vcharacteristics of junction arrays containing up to 1000 junctions highlight the excellent uniformity and scalability of our process. Furthermore, by introducing a RIE pre-etch before BOE treatment to remove most of the SiO2insulator, we have suppressed dielectric loss and increased the coherence time of the Nb-based transmon qubit by almost 10 times, achieving a quality factor comparable to state-of-the-art Nb-based qubits on sapphire substrates. Given its compatibility with silicon technology, our method paves the way for the integration of multi-qubit processors and the co-fabrication of complex quantum circuits.