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Effect of bottom electrode stress on the annealing stability of Nb/Al-AlOx/Nb junctions

Hongchao WANG, Guixiang HE, Liliang Ying, Linxian MA, Feng Zhou, Weifeng SHI, Hui XIE, Ling Wu, Wei PENG

Published Apr 1, 2026• 1 citation
Publisher

Abstract

The Nb/Al-AlOx/Nb Josephson junction serves as the core component of mainstream low-temperature superconducting devices. With the growing demand for scaling up superconducting circuits, increasing the process temperature has become a key technical direction. However, during higher-temperature processing, the difference in the coefficient of thermal expansion between niobium and the substrate introduces significant thermal stress, which degrades junction quality. To mitigate the adverse effects of thermal stress, this paper proposes a stress pre-compensation method: by pre-tuning the residual stress of the bottom niobium electrode, the thermal stress generated in subsequent high-temperature steps is counteracted, thereby maintaining the total stress in the bottom electrode at a low level. In experiments, a series of Josephson junctions with different bottom-electrode stresses were electrically characterized at 4.2 K before and after annealing. The results show that controlling the residual stress of the bottom electrode within a specific tensile range can improve the post-annealing yield. After annealing at 250 ℃ for 30 min, junctions with an initially tensile-stressed bottom Nb electrode exhibited approximately a 14% higher yield compared to those with compressive stress. This trend was also verified in the annealing process of Nb/Al-AlOx-Al*/Nb Josephson junctions.

DOI
10.3724/jfmd.2602030

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The Nb/Al-AlOx/Nb Josephson junction serves as the core component of mainstream low-temperature superconducting devices. With the growing demand for scaling up superconducting circuits, increasing the process temperature has become a key technical direction. However, during higher-temperature processing, the difference in the coefficient of thermal expansion between niobium and the substrate introduces significant thermal stress, which degrades junction quality. To mitigate the adverse effects of thermal stress, this paper proposes a stress pre-compensation method: by pre-tuning the residual stress of the bottom niobium electrode, the thermal stress generated in subsequent high-temperature steps is counteracted, thereby maintaining the total stress in the bottom electrode at a low level. In experiments, a series of Josephson junctions with different bottom-electrode stresses were electrically characterized at 4.2 K before and after annealing. The results show that controlling the residual stress of the bottom electrode within a specific tensile range can improve the post-annealing yield. After annealing at 250 ℃ for 30 min, junctions with an initially tensile-stressed bottom Nb electrode exhibited approximately a 14% higher yield compared to those with compressive stress. This trend was also verified in the annealing process of Nb/Al-AlOx-Al*/Nb Josephson junctions.
Nb/Al-AlOx/Nb Josephson junctions are widely used in superconducting quantum interference devices and rapid single flux quantum (RSFQ) circuits. Very large-scale RSFQ integration often has a strict requirement on wafer-scale junction qualities. In particular, Nb film stress in Nb/Al-AlOx/Nb trilayer based Josephson junctions is a critical factor affecting their qualities. In this work, we develop a multi-step sputtering process to prepare Nb films with different combinations of stress and roughness to investigate the correlation between Nb film stress and junction quality. In particular, this method allows us to prepare Nb films with almost the same roughness but different stress, a key factor to study solely the influence of stress on junction qualities. Our measurements indicate that within a very tight range of film roughness (less than 2 nm), tensile film stress is found to decrease the quality of Nb/Al-AlOx/Nb Josephson junctions and larger film roughness has a positive effect on junction quality. By decreasing the total tensile stress and increasing the film roughness properly, we fabricated Nb/Al-AlOx/Nb Josephson junctions with a high quality factor characterized by Rsg/RN(30 on average). The minimum size of junctions was 1 μm.
Reproducibility of Al/AlO x /Al Josephson junctions is a challenge for scaling up superconducting quantum processors. The frequency uncertainty of the transmon qubits arising from the fabrication process is attributed to deviations in the Josephson junction microstructure and electrical properties. Here, we present a solution for this problem using the post-fabrication Josephson junction thermal annealing process. The developed thermal post-exposure method allows not only to increase the junction resistance by 175%, but also to decrease by 60% with a step of 10% in R n , which opens up new possibilities for tuning the frequency of qubits. The resistance is shown to be strongly temperature dependent, and is weakly dependent on the holding time. The linear dimensions of the electrodes and the sidewalls contribution to the total JJ area also have a significant impact on the final resistance after annealing. Finally, a theoretical model of the structure modification in a tunnel barrier with changes in oxygen concentration gradient is proposed. The proposed thermal annealing approach can be used to form stable and reproducible tunnel barriers and scalable frequency trimming for widely used fixed-frequency transmon qubits.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
The Josephson junction is a crucial element in superconducting devices, and niobium is a promising candidate for the superconducting material due to its large energy gap relative to aluminum. AlOx has long been regarded as the highest quality oxide tunnel barrier and is often used in niobium-based junctions. Here, we propose ZrOx as an alternative tunnel barrier material for Nb electrodes. We theoretically estimate that zirconium oxide has excellent oxygen retention properties and experimentally verify that there is no significant oxygen diffusion leading to NbOx formation in the adjacent Nb electrode. We develop a top–down, subtractive fabrication process for Nb/Zr–ZrOx/Nb Josephson junctions, which enables scalability and large-scale production of superconducting electronics. Using cross-sectional scanning transmission electron microscopy, we experimentally find that depending on the Zr thickness, ZrOx tunnel barriers can be fully crystalline with chemically abrupt interfaces with niobium. Further analysis using electron energy loss spectroscopy reveals that ZrOx corresponds to tetragonal ZrO2. Room temperature characterization of fabricated junctions using Simmons’ model shows that ZrO2 exhibits a low tunnel barrier height, which is promising in merged-element transmon applications. Low temperature transport measurements reveal sub-gap structure, while the low-voltage sub-gap resistance remains in the megaohm range.
To avoid degradation of circuit performance, fabrication processes for niobium-based superconductive electronics are typically limited to temperatures below 150°C. In this study, we investigated protective dielectric capping layers that preserve the superconducting properties of Niobium (Nb) wiring at processing temperatures as high as 400°C. To assess the thermal stability of Nb films, 400 nm thick Nb layers were deposited on oxidized silicon wafers and were either left uncapped or were intentionally capped with selected dielectric materials. The samples were subjected to post-deposition annealing in an argon atmosphere for comparison. Samples were annealed up to 450°C, and changes in room temperature sheet resistance were used as a proxy for film degradation and checked with cryogenic measurements of samples annealed up to 400°C. A sharp increase in room temperature sheet resistance, and a resulting decrease in residual resistivity ratio was observed in pristine Nb films above 300°C. We found that theex-situdeposition of insulating covering (“cap”) reduces the onset of degradation. Notably, silicon oxide (SiO_x\_{x}_x) capping shows significant improvement and silicon nitride (Si_x\_{x}_xN_y\_{y}_y) capped samples exhibit minimal changes in resistance across the full annealing range. These results suggest that Si_x\_{x}_xN_y\_{y}_yencapsulation as a dielectric “cap” preserves superconductive properties and offers an expanded thermal budget for Nb-based superconductive electronics, with implications for multilayer integration and scalable fabrication.
Understanding the aging behavior of Josephson junctions and the effect of annealing on junction resistances is important in building large-scale superconducting quantum processors. Here we study the effects of aging of Al/AlOx/Al Josephson junctions under different storage conditions from immediately after fabrication up to 2 to 3 months. We find that the aging curve follows a logarithmic curve, with the aging amplitude mainly determined by fabrication conditions and the aging rate determined by both fabrication and storage conditions. Junctions stored at ambient laboratory conditions aged faster compared to junctions stored in a nitrogen atmosphere or vacuum, with the aging speed appreciably changes when the storage condition changed. We also compared the effect of thermal annealing under nitrogen environment with annealing under ambient conditions up to 250∘^\circ∘C. We find that under nitrogen environment, the resistances decreased at all temperatures tested, while under ambient environment the resistances increased at 200∘^\circ∘C and decreased at 250∘^\circ∘C instead. We were unable to decrease the resistance below the initial-time resistance, suggesting a lower limit on the range of resistance tuning.