Design and Measurement of zero static power SFQ circuit

T. Nishigai, Shohei Yamada, Nobuyuki Yoshikawa

Mark H. Volkmann, Anubhav Sahu, Coenrad Johann Fourie +1 more

We present the design and results of experimental verification methods for ultra-low-power digital circuits based on the recently introduced energy-efficient single flux quantum (eSFQ) logic. Similar to another low-power SFQ logic, ERSFQ, eSFQ circuits make use of superconducting dc bias current dividers and thus avoid static power dissipation. As a result, per-gate power dissipation is reduced by two orders of magnitude as compared to conventional rapid single flux quantum and static power dissipation is zero. The eSFQ circuits are fabricated using the HYPRES standard 4.5 kA/cm2process. We integrate a low-pass analog-to-digital modulator with our eSFQ deserializer to enable testing at high speed. In this paper, we demonstrate the viability and performance metrics of eSFQ circuits through functional and high-speed tests. Specifically, we confirmed correct operation and present measured parameter margins.

Kazunori Miyahara, Shuichi Nagasawa, H. Hasegawa +3 more

Mingfan Chen, Xue Zhang, Junrong Zhao +4 more

To improve circuit density and minimize static power dissipation in Single Flux Quantum (SFQ) circuits, this work investigates the application of inductively biased, unshunted Josephson transmission lines (JTLs) which achieve zero static power, compared with regular resistively biased JTLs. Both simulation and experiment results confirm that unshunted JTLs can reliably propagate SFQ pulses with a bias current margin larger than 50%. Based on this, a new fabrication process has been developed featuring eight niobium (Nb) layers, including two Nb/Al-AlOx/Nb junction layers, a dedicated bias-inductor layer, and dual DC-power layers. The vertical functional separation allows 2 active layers. The 1stactive layer uses conventional shunted JJs for logic gates, while the 2nduses unshunted JTLs with inductive bias. This configuration eliminates static power in the interconnect network and simplifies thermal management in stacked Rapid SFQ (RSFQ) architectures. A ten-stage unshunted JTL chain and a hybrid half-adder were designed and demonstrated. Measurements show a 66.7% reduction in static power and a 64.7% reduction in area compared with the Chinese Academy of Scienceconventional single-JJ-layer process. These results verify, for the first time, that inductively biased unshunted interconnects can be monolithically integrated with standard RSFQ logic, offering a scalable path toward ultra-dense, lower-power multilayer superconducting circuits.

Takumi Takinami, Ito Masato, Kitayama Atsushi +2 more

Yuki Yamanashi, T. Nishigai, Nobuyuki Yoshikawa

A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.