A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.
We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.
The digital circuits in a superconducting quantum computer must be cooled to cryogenic temperatures in a dilution refrigerator for control and information readout of the qubit information. Because the dilution refrigerator's heat capacity is limited, extremely low-power digital circuits are required. Single-flux-quantum (SFQ) circuits and Josephson photomultipliers (JPMs) are expected to serve as control and readout circuits for superconducting quantum computers. These circuits generate minimal heat, but further reductions in power consumption are required to make it possible to build larger, more scalable faulttolerant quantum computers (FTQC). In this paper, we propose a low-power and reliable peripheral circuit for JPM-based qubit readout utilizing an SFQ counter circuit. The counter performs majority voting across repeated readouts, significantly improving the reliability of the JPM readout process. Additionally, we quantitatively evaluate switching errors in SFQ circuits using Josephson junctions with low-critical current values. By integrating these circuit techniques and simulation results, we find that the proposed approach achieves a 90% reduction in power consumption while effectively suppressing the increase in readout error.
Abstract The use of high-frequency input signals from room-temperature microwave sources makes it difficult to scale up the number of quantum bits in universal quantum computers. To address this issue, superconducting single flux quantum (SFQ) integrated circuits are being explored as suitable candidates for qubit manipulation in universal quantum computers. This paper deals with a scalable SFQ qubit control circuit (SQCC) structure that requires only low-frequency input. The circuit mainly consists of a pulse generator and a counter, that output the SFQ pulse train with adjustable frequency and a controllable number of pulses, which is applicable to control single-qubit Clifford operations. The design of low-voltage rapid single flux quantum (LV-RSFQ) and energy-efficient rapid single flux quantum (ERSFQ) for the SQCC achieves low power consumption and provides a basis for scaling up SQCC to control more qubits. The proposed circuits are fabricated under the SIMIT-Nb03 process and successfully pass test verification. The achieved test results reveal that the adjustable output frequency ranges of the SQCC based on the LV-RSFQ and ERSFQ designs in order are [2.40, 8.11] GHz and [4.81, 5.14] GHz. In the operating frequency range, the circuit is able to generate the correct number of SFQ pulses under control. The controllable number range is from 1 to 128. When the circuits operate at 5 GHz, the total power consumptions of the above circuits in order are 23.88 μW and 6.2 μW. All input signals are low-frequency signals, which frees the control of large-scale qubits from limitations caused by high-frequency inputs produced by room-temperature microwave sources.
In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents (
Icvalues) of the Josephson junctions (JJs), or the bias voltage (
Vb). The shifts and spreads of timing parameter fluctuations when
Icand
Vbwere lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after
Icwas lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered
Vbvalues were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered
Icor
Vbto 6.25% of their conventional values, and the energy reduction after lowering of
Vbwas 26% better than that after lowering of
Ic. Moreover, if a small error rate (for example
10−6) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.
Rapid single flux quantum (RSFQ) electronics is based on the Josephson junction as an active switching element. In standard RSFQ circuits its switching energy is much lower than the static power consumption caused by the resistive current distribution network. Due to this thermal heating of the chip, the maximum number of junctions on a single chip is limited to about 1 million. The frequency-dependent contribution to power dissipation from junction switchings is only about 2 percent of the static one. This fact limits the direct construction of VLSI systems for high-performance computing as well as small-scale circuit applications in the vicinity of ultra-sensitive detectors or even quantum circuits. We present an assessment of different approaches for reducing the static power consumption by investigating the potential of inductive bias distribution networks as well as reduced critical currents. We analyse the operation stability of simple digital circuits with 5 times smaller critical currents at 4.2 K. The combination of the reduced critical currents and inductive biasing can provide digital superconductive circuits with significantly reduced static power consumption.