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High-speed demonstration of low-power 1 k-bit shift-register memories using LR-biasing SFQ circuits

Toshihiro Takahashi, Ryo Numaguchi, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Jan 1, 2016• 8 citations
Publisher

Abstract

We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.

DOI
10.1587/elex.13.20160074

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We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.
A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.
We propose a new inductive- and resistive- (LR) biased low-power single-flux quantum (SFQ) circuit that has a dynamic resetting mechanism of the bias current. Because the bias current returns to the initial state rapidly by switching of a Josephson junction in the bias circuit after circuit operation, the operating frequency of the LR-biased SFQ circuit can be improved. We simulated a Josephson transmission line (JTL) that employs the proposed biasing scheme and evaluated the bias current recovery time. Circuit simulation results show that the bias current recovery time of the proposed circuit is improved by 10-20% compared to that of the conventional LR-biased JTL. We have designed and measured a 10-stage JTL and an 8-bit concurrent-flow shift register (SR) with the proposed biasing scheme. We have experimentally demonstrated operation of the JTL with the bias margin of ±29.4% at the operating frequency of up to 70.4 GHz and operation of the 8-bit SR up to 12.3 GHz by the on-chip high-speed test.
Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.
We demonstrate rapid single-flux-quantum (RSFQ) circuits with reduced energy consumption by lowering the driving voltages and critical currents of Josephson junctions (JJs). At lowered voltages, the energy statically consumed by bias resistors (which is dominant in RSFQ circuits) is reduced. In addition, we show that when RSFQ circuits are driven by lowered constant voltages, the dynamic energy consumption resulting from the switching of JJs is reduced because of the suppression of the amplitudes of the signal voltage pulses, even though the switching speed becomes slower. Utilization of miniaturized JJs with smaller critical currents also leads to the reduction of static and dynamic energy consumption without decreasing the switching speed. We have designed and tested ultra-low-energy 8-bit shift registers, and verified the correctness of high-speed operations up to 18 GHz. The average energy consumption, including that at the bias resistors, was measured at 4.0 aJ/bit, which represents an energy efficiency two orders of magnitude better than that of standard RSFQ circuits.
We have demonstrated rapid-single-flux-quantum (RSFQ) circuits with reduced power consumptions by lowering bias voltages and critical currents. The power consumption including a power consumption of a bias resistor is measured to be around 1 nW/JJ in 8-bit shift registers, while the operating frequency ranges from 7.5 GHz to 20 GHz. we lower bias voltages applied to RSFQ circuits. The values of bias resistances are proportional to bias voltages. At lowered bias voltages, the power consumption of the bias resistor is reduced. When a voltage begins to be generated at a Josephson junction, the net current provided to the junction and to the shunt resistor is decreased. As a result, the magnitude of the voltage is suppressed, and the power consumption of the shunt resistor is reduced. The power energy-delay product is about 70 times smaller and the the energy-delay product is more than 13 times smaller than that of the conventional RSFQ circuits. Low poewer SFQ circuits are superior in terms of energy-delay product to semiconductor circuits though the power consumption of SFQ cicuits contains the refrigerating machine.
In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift registers, which are one candidate to solve the memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift register file as a demonstration of the SFQ shift register memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm −2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift register at high speed. A tested dc bias margin at 20 GHz is ±5%.