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IEEE International Superconductive Electronics Conference (ISEC)

Analysis of computational energy efficiency in single-flux-quantum electronics by implementing an integer-based hardware-algorithm

Qiuyun Xu, Y. Shimamura, Yuki Yamanashi, Nobuyuki Yoshikawa, Thomas Ortlepp

Published Jul 1, 2013• 2 citations
Publisher

Abstract

We designed and implemented a single-flux-quantum (SFQ) based hardware-algorithm known as the 3n+1 conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator and a central processor. This design can perform with a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW based on the AIST 10 kA/cm2advanced Nb process. The power consumption was further reduced by using an LR-biasing approach.

DOI
10.1109/isec.2013.6604280

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We designed and implemented a single-flux-quantum (SFQ) based hardware-algorithm known as the 3n+1 conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator and a central processor. This design can perform with a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW based on the AIST 10 kA/cm2advanced Nb process. The power consumption was further reduced by using an LR-biasing approach.
The Collatz conjecture asserts that by a repeated iteration rule, the operation starting from any positive integer n, eventually produces the value of “1.” The main contribution of this paper is to demonstrate a single-flux-quantum (SFQ)-based hardware algorithm that performs an exhaustive search to verify the Collatz conjecture. The circuit consists of a 16-bit integer register, a high-frequency clock generator, and a central processor. This design can perform at up to a maximum clock frequency of 90 GHz with a total power consumption of about 0.85 mW in simulation, based on the AIST 10 kA/cm2advanced Nb process. An LR-biasing approach further reduces the power consumption, whereas the computing speed can be accelerated by a factor of 20 when accelerating approaches are adopted. The assessments show that our design can process 2 × 107numbers every second with an energy efficiency of about 5 × 1010numbers per Joule.
A single-flux-quantum (SFQ) circuit is thought to be very suitable as a peripheral circuit for superconducting quantum bits (qubits), which can manipulate and detect the qubit state at a temperature state similar to qubits. Even though the power consumption of SFQ circuits is extremely small, it is still sufficient to heat the substrate at a temperature below 1 K. We have investigated and demonstrated low-power SFQ circuits for this application, using the LR-loading technique, which can reduce the static power consumption of the SFQ circuits. Simulation results show that the ratio of the switching speed to the time constant of the bias circuit is important for the stable operation of low-power SFQ circuits. The static power consumption of SFQ circuits can be reduced to the same order as the dynamic power consumption through optimization of the circuit parameters. We have designed and tested a low-power SFQ clock generator using the LR-loading technique and confirmed its stable operation at 4.2 K, where the power consumption is reduced by 93% compared with ordinary biased circuits.
We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.
Our aim is the development of a high-speed and low-power-dissipation fast Fourier transform processor using single-flux-quantum circuits. We have been working on the development of the core processing circuit, a butterfly processing circuit. In our previous study, we designed an integer-type butterfly processing circuit using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the local clock frequency of 50 GHz. In this study, we propose a configuration for signed-number calculation based on the two's complement conversion. We designed a butterfly processing circuit for signed numbers by using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the maximum local clock frequency of 51.6 GHz.
We have been working on the development of a high-speed fast Fourier transform (FFT) processor using single-flux-quantum (SFQ) logic circuits. In our previous studies, we designed and demonstrated a 4-bit butterfly processor, a data-shuffling circuit, and a twiddle factor ROM for 4-bit 8-point FFT using the AIST 10 kA/cm2Nb advanced process 2 at maximum frequencies of 51.6, 59.5, and 51.5, respectively. In this study, to complete the FFT processor design, we designed and demonstrated residual component circuits called a rounding circuit and a data buffer at a target frequency of 50 GHz. We also designed and experimentally confirmed the operation of an SFQ-based single-chip FFT processor integrating all the component circuits.
Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 μW per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.