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IEEE Transactions on Applied Superconductivity

High-Speed Operation of an SFQ Butterfly Processing Circuit for FFT Processors Using the 10 kA/cm2 Nb Process

Y. Sakashita, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Dec 22, 2014• 13 citations
Publisher

Abstract

Our aim is the development of a high-speed and low-power-dissipation fast Fourier transform processor using single-flux-quantum circuits. We have been working on the development of the core processing circuit, a butterfly processing circuit. In our previous study, we designed an integer-type butterfly processing circuit using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the local clock frequency of 50 GHz. In this study, we propose a configuration for signed-number calculation based on the two's complement conversion. We designed a butterfly processing circuit for signed numbers by using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the maximum local clock frequency of 51.6 GHz.

DOI
10.1109/tasc.2014.2384833

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IEEE Transactions on Applied Superconductivity•Jan 7, 2011•13 citations
Our aim is the development of a high-speed and low-power-dissipation fast Fourier transform processor using single-flux-quantum circuits. We have been working on the development of the core processing circuit, a butterfly processing circuit. In our previous study, we designed an integer-type butterfly processing circuit using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the local clock frequency of 50 GHz. In this study, we propose a configuration for signed-number calculation based on the two's complement conversion. We designed a butterfly processing circuit for signed numbers by using the AIST 10 kA/cm2Nb advanced process and confirmed its high-speed operation at the maximum local clock frequency of 51.6 GHz.
We are developing a fast Fourier transform (FFT) processor using high-speed and low-power single-flux-quantum (SFQ) circuits. Our main concern is the development of an SFQ butterfly processing circuit, which is the core processing circuit in the FFT processor. In our previous study, we have confirmed the complete operation of an integer-type butterfly processing circuit using the AIST 2.5 kA/cm2 Nb standard process at the frequency of 25 GHz. In this study, we have designed an integer-type butterfly processing circuit using the AIST 10 kA/cm2 Nb advanced process and confirmed its high-speed operation at the maximum frequency of 50 GHz.
We are developing a high-speed FFT processor using single- flux-quantum (SFQ) logic circuits. In our previous studies we have designed and demonstrated a 4-bit butterfly processor using the AIST 10 kA/cm2Nb Advanced Process 2 (ADP2) at the frequency of 51.6 GHz, which is the main circuit of the FFT processor. In this study, we investigated the architecture of the SFQ FFT processor. We also designed the component circuits for on-chip SFQ FFT system using ADP2. We demonstrated the component circuits, the data-shuffling circuit and twiddle factor ROM for 4-bit 8-point FFT at the maximum frequency of 59.5 GHz and 51.5 GHz, respectively. The calculation time for a 32-bit 1024-point FFT using a pipelined SFQ FFT processor was estimated to be 6.2 μs.
We have been working on the development of a high-speed fast Fourier transform (FFT) processor using single-flux-quantum (SFQ) logic circuits. In our previous studies, we designed and demonstrated a 4-bit butterfly processor, a data-shuffling circuit, and a twiddle factor ROM for 4-bit 8-point FFT using the AIST 10 kA/cm2Nb advanced process 2 at maximum frequencies of 51.6, 59.5, and 51.5, respectively. In this study, to complete the FFT processor design, we designed and demonstrated residual component circuits called a rounding circuit and a data buffer at a target frequency of 50 GHz. We also designed and experimentally confirmed the operation of an SFQ-based single-chip FFT processor integrating all the component circuits.
The Fast Fourier Transform (FFT) is extensively used in image processing, wireless communication, and other applications. Some applications that involve very complicated, real-time FFT processing require specialized hardware for performing high-speed FFT processing. We have been developing high-speed FFT processors based on single flux quantum (SFQ) circuit technology. In this study, we developed a butterfly processing element for FFT processors that uses SFQ circuits. The butterfly processing element consists of complex number adders, subtractors, and multipliers. The circuit structure was modified compared to that of previous SFQ FFT processors to reduce latency. Several buffer circuits were inserted in the multipliers to compensate for timing jitter accumulation and discrepancies due to signal propagation delay. We designed and implemented a four-bit bit-serial butterfly processing element that contains 5763 Josephson junctions using the ISTEC Nb 2.5-kA/cm2standard 2 process and the CONNECT cell library. Correct operation of the butterfly processing unit was experimentally confirmed at a clock frequency of 25 GHz.
A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence at high speed. FFT can convert a signal from time domain to frequency domain, and is wildly used in digital signal processing field. In this paper, a high-speed, low-power FFT processor is demonstrated up to 47.8GHz with the measured power consumption of 5.3mW, using single-flux quantum (SFQ) logic. This is the first complete FFT processor implementation using superconducting technology, performing 8-point 7-bit FFT in a bit-serial computing manner. The test chip fabricated using a 1.0 μm 9-layer process consists of 17 455 Nb/AlOx/Nb Josephson junctions (JJs), rendering itself the largest superconducting digital circuit capable of iterative data computing. The correct operation of the chip has been experimentally confirmed at a maximum operating frequency of 47.8GHz (word speed 8GHz) by conducting on-chip high-speed testing.
Design and Implementation of Component Circuits of an SFQ Half-Precision Floating-Point Adder Using 10-kA/cm2^{2}2 Nb Process
We have been developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. The SFQ floating-point adder (FPA) is one of the principal and most complicated circuit blocks in an LSRDP. In this study, we designed and implemented component circuits of an SFQ bit-serial half-precision FPA using the cell library for a 10-kA/cm2Nb process and performed on-chip high-speed tests. We demonstrated correct operation of the four-bit shifter for the significand at the clock frequencies of up to 76 GHz. The dependence of the measured DC bias margin on the operating frequency agrees reasonably well with the margin calculated using a digital simulation. The operation of the normalizer for the significand has been also confirmed at low speeds.