IEICE Technical Report; IEICE Tech. Rep.

Analysis of Interference for Low-Voltage-Driven SFQ Circuits

Takumi Takinami, Ito Masato, Kitayama Atsushi, Tanaka Masamitsu, Fujimaki Akira

Published Jan 17, 2013• 0 citations

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IEICE Technical Report; IEICE Tech. Rep.

Analysis of Interference for Low-Voltage-Driven SFQ Circuits

Takumi Takinami, Ito Masato, Kitayama Atsushi, Tanaka Masamitsu, Fujimaki Akira

Published Jan 17, 2013• 0 citations

OpenAlex

Related papers

△Evaluation of Interference in Low-Voltage RSFQ Circuits

Takumi Takinami

The Japan Society of Applied PhysicsFeb 13, 20130 citations

Design of Circuits Controlling Dependence of Signal Propagation Time on Bias Voltage for Expanding the Operating Margin of SFQ Circuits

Mikio Otsubo, Yuki Yamanashi, Nobuyuki Yoshikawa

IEICE Technical Report; IEICE Tech. Rep.Jul 12, 20120 citations

低電圧駆動SFQ回路における干渉の解析 : 招待講演

Takumi Takinami, MASATO ITO, Atsushi KITAYAMA +6 more

Jan 1, 20130 citations

Investigation of Timing Parameters in Single-Flux-Quantum Circuits Using Low Critical-Current Junctions and Low Bias Voltages

Manami Kuniyoshi, Ken Murase, Ikki Nagaoka +4 more

In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents ( $I_{\mathrm{c}}$ values) of the Josephson junctions (JJs), or the bias voltage ( $V_{\mathrm{b}}$ ). The shifts and spreads of timing parameter fluctuations when $I_{\mathrm{c}}$ and $V_{\mathrm{b}}$ were lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after $I_{\mathrm{c}}$ was lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered $V_{\mathrm{b}}$ values were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered $I_{\mathrm{c}}$ or $V_{\mathrm{b}}$ to 6.25% of their conventional values, and the energy reduction after lowering of $V_{\mathrm{b}}$ was 26% better than that after lowering of $I_{\mathrm{c}}$ . Moreover, if a small error rate (for example $10^{-6}$ ) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents ($I_{\mathrm{c}}$values) of the Josephson junctions (JJs), or the bias voltage ($V_{\mathrm{b}}$). The shifts and spreads of timing parameter fluctuations when$I_{\mathrm{c}}$and$V_{\mathrm{b}}$were lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after$I_{\mathrm{c}}$was lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered$V_{\mathrm{b}}$values were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered$I_{\mathrm{c}}$or$V_{\mathrm{b}}$to 6.25% of their conventional values, and the energy reduction after lowering of$V_{\mathrm{b}}$was 26% better than that after lowering of$I_{\mathrm{c}}$. Moreover, if a small error rate (for example$10^{-6}$) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.

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Springer eBooksJan 1, 20000 citations

I_{\mathrm{c}}

values) of the Josephson junctions (JJs), or the bias voltage (

V_{\mathrm{b}}

). The shifts and spreads of timing parameter fluctuations when

I_{\mathrm{c}}

and

V_{\mathrm{b}}

were lowered were numerically analyzed, with consideration of thermal noise at 4.2 K. The timing behaviors after

I_{\mathrm{c}}

was lowered were relatively simple, being based on the signal-to-noise ratio, whereas those for lowered

V_{\mathrm{b}}

values were complicated because of the dynamic behaviors of JJs driven at reduced voltage. The simulation results imply that the operating frequencies decreased because the timing windows narrowed, but the highest energy efficiency was obtained when we lowered

I_{\mathrm{c}}

V_{\mathrm{b}}

to 6.25% of their conventional values, and the energy reduction after lowering of

V_{\mathrm{b}}

was 26% better than that after lowering of

I_{\mathrm{c}}

. Moreover, if a small error rate (for example

10^{-6}

) is acceptable, further improvement in energy efficiency would be expected at significantly higher clock frequencies than would be the case if the SFQ circuit must exhibit error-free operation.