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Springer eBooks

Fundamental Research Toward SFQ-Integrated Circuits

Akira Fujimaki, Yasutoshi Suzuki, Hiroaki HASEGAWA, Futoshi Furuta, Hisao Hayakawa

Published Jan 1, 2000• 0 citations
Publisher
DOI
10.1007/978-4-431-66877-0_322

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A superconductive single flux quantum (SFQ) digital integrated circuit with an optical data input has been demonstrated at the system level of 40 Gbit/s for the first time. A uni travelling carrier photodiode (UTC-PD) and an SFQ circuit chip, on which 40 Gbit/s I/O interfaces were integrated, were packaged on a cold stage (4–6 K) of a cryocooler system. The UTC-PD's output was connected to an input port of the SFQ circuit with a Cu coaxial cable. From room temperature, a 40 GHz clock was supplied to the SFQ circuit while 40 Gbit/s optical data were supplied to the UTC-PD. The SFQ circuit operated correctly with the optical 40 Gbit/s data. The measured bit error rate was less than 10−13 for 1.2 mW optical PRBS 7 input at 40 Gbit/s.
Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.