Challenges in the Realization of SFQ Digital Circuits

Pascal Febvre, Romain Collot, N. de Leo +3 more

Kazunori Miyahara, Shuichi Nagasawa, H. Hasegawa +3 more

Seda Demirhan, Ali Bozbey

Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-density CMOS memories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit and SRAM module and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm2STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm × 1.60 mm.

Boyko Dimov, Thomas Ortlepp, Friedrich Uhlmann

Within the classical Rapid Single-Flux Quantum (RSFQ) digital designs, the superconductive phase dropping necessary for the optimal SFQ data processing is realized with short sections of transmission lines serving as lumped inductances. This approach meets several hard restrictions about some promising future RSFQ applications requiring a drastic reduction of the junctions' critical currents. In this paper, we analyse these restrictions, and present an alternative and experimentally verified technique for superconductive phase dropping, which is compatible with any RSFQ fabrication technology. This technique provides compact and robust RSFQ digital circuits with highly improved fabrication yield.

Akira Fujimaki, Yasutoshi Suzuki, Hiroaki HASEGAWA +2 more

Jason Walter, Adam C. Weis, Kan-Ting Tsai +6 more

As quantum computing processors increase in size, there is growing interest in developing cryogenic electronics to overcome significant challenges to system scaling. Single flux-quantum (SFQ) circuits offer a promising alternative to remote, bulky, and power-hungry room temperature electronics. To meet the need for digital qubit control, readout, and co-processing, SFQ circuits must be adapted to operate at millikelvin temperatures near quantum processors. SEEQC's SFQuClass digital quantum management approach proximally places energy-efficient SFQ (ERSFQ) circuits and qubits in a multi-chip module. This enables extremely low power dissipation, compatible with a typical dilution cryostat's limited cooling power, while maintaining high processing speed and low error rates. We report on systematic testing from 4 K to 10 mK of a comprehensive set of ERSFQ cells, as well as more complex circuits such as programmable counters and demultiplexers used in digital qubit control. We compare the operating margins and error rates of these circuits and find that, at millikelvin, bias margins decrease and the center of the margins (i.e., the optimal bias current value) increases by ~15%, compared to 4.2 K. The margins can be restored by thermal annealing by reducing Josephson junction (JJ) critical current Ic. To provide guidance for how circuit parameters vary from 4.2 K to millikelvin, relevant analog process control monitors (PCMs) were tested in the temperature range of interest. The measured JJ critical current (of the PCM JJ arrays) increases by ~15% when decreasing temperature from 4.2 K to millikelvin, in good agreement with both theory and the empirically measured change in the center of bias margins for the tested digital circuits.