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IEICE Transactions on Electronics

Design of SFQ Circuits and Their Measurement

Kazunori Miyahara, Shuichi Nagasawa, H. Hasegawa, Tatsunori Hashimoto, Hideo Suzuki, Youichi Enomoto

Published Mar 1, 2002• 0 citations
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In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.

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In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.

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Design and Fabrication of All-NbN SFQ Circuits for SSPD Signal Processing

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We have developed an all-NbN integrated circuit technology for future integration of single flux quantum (SFQ) circuit with superconducting single-photon detector array. The all-NbN integrated circuits consist of epitaxial NbN/AlN/NbN tunnel junctions fabricated on single-crystal MgO substrates, Mo shunt resistors and 500-nm-thick NbN ground plane on the top. Critical current density and sheet resistance of the Mo resistor were set at 2.5 kA/cm2and 1.2 Ω, respectively. Current uniformity of the NbN/AlN/NbN tunnel junctions was measured to be σ = 3% for 3 μm × 3 μm junction size. The NbN-based SFQ logic cells were designed for and tested at 4.2 K. We actually measured circuit inductances of the fabricated SFQ cells. Circuit simulation revealed that the measured circuit inductances in the fabricated SFQ cells should allow operating margins of more than +/-20%.

IEEE Transactions on Applied Superconductivity•Dec 20, 2012•29 citations
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.
We have developed an all-NbN integrated circuit technology for future integration of single flux quantum (SFQ) circuit with superconducting single-photon detector array. The all-NbN integrated circuits consist of epitaxial NbN/AlN/NbN tunnel junctions fabricated on single-crystal MgO substrates, Mo shunt resistors and 500-nm-thick NbN ground plane on the top. Critical current density and sheet resistance of the Mo resistor were set at 2.5 kA/cm2and 1.2 Ω, respectively. Current uniformity of the NbN/AlN/NbN tunnel junctions was measured to be σ = 3% for 3 μm × 3 μm junction size. The NbN-based SFQ logic cells were designed for and tested at 4.2 K. We actually measured circuit inductances of the fabricated SFQ cells. Circuit simulation revealed that the measured circuit inductances in the fabricated SFQ cells should allow operating margins of more than +/-20%.