The design of single flux-quantum (SFQ) circuits requires well-defined inductances. In many cases these are created by irregular geometries and a computer-aided design tool is necessary for inductance calculations. This becomes a challenging task in cases where no ground plane is used and thus three-dimensional calculations are required. For this purpose, InductEx was developed and verified successfully for simple structures. In this work we take the next step and demonstrate the applicability of InductEx to the design of rapid single flux-quantum (RSFQ) cells. We use InductEx for inductance modeling as an integral part of the design cycle for an RSFQ cell with flux quantum transfer via mutual inductance and for a DC-reprogrammable logic circuit with similar inductive coupling. The relation between coupling factor and self-inductance is optimized in the circuit layout. All coupling structures are duplicated in SQUID modulation test circuits to measure and verify calculation accuracy. We find excellent agreement between the calculated and measured inductance values. Furthermore, the operational area of the basic cell is determined and compared with similar investigations reported earlier. Based on this comparison we conclude that InductEx is a valuable inductance design tool, and that mutual coupling in structures using ground plane holes and RSFQ-compatible self-inductances can be modeled and designed reliably.
The design of single flux-quantum (SFQ) circuits requires well-defined inductances. In many cases these are created by irregular geometries and a computer-aided design tool is necessary for inductance calculations. This becomes a challenging task in cases where no ground plane is used and thus three-dimensional calculations are required. For this purpose, InductEx was developed and verified successfully for simple structures. In this work we take the next step and demonstrate the applicability of InductEx to the design of rapid single flux-quantum (RSFQ) cells. We use InductEx for inductance modeling as an integral part of the design cycle for an RSFQ cell with flux quantum transfer via mutual inductance and for a DC-reprogrammable logic circuit with similar inductive coupling. The relation between coupling factor and self-inductance is optimized in the circuit layout. All coupling structures are duplicated in SQUID modulation test circuits to measure and verify calculation accuracy. We find excellent agreement between the calculated and measured inductance values. Furthermore, the operational area of the basic cell is determined and compared with similar investigations reported earlier. Based on this comparison we conclude that InductEx is a valuable inductance design tool, and that mutual coupling in structures using ground plane holes and RSFQ-compatible self-inductances can be modeled and designed reliably.
Single-flux-quantum (SFQ) digital circuits are mostly based on cells that rely on reliable foundry processes that make use of a superconducting ground plane as a reference for the active elements and the microstrip line interconnects. The quantum of magnetic flux h/2e, associated with the binary information, corresponds to a magnetic field energy density that needs to be localized in space to limit interactions between adjacent cells. In other words, mutual inductances can harm the proper behaviour of circuits unless they are taken carefully into account during the design phase. We studied extensively the Josephson transmission line cell with different geometrical configurations of the ground plane and bias pads. We found with the use of InductEx that the return current sometimes follows paths that are far from what intuition tells, which can lead to nonoptimized designs. In this paper, we emphasize the limitations due to the presence of external or internal magnetic fields. Then, we compare obtained performances with the ones with optimized geometries for which the presence of the magnetic field is taken into account from the design phase.
We suggest a new design of rapid single flux quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. Small inductances of about 10 pH, obligatory for RSFQ circuits, are formed as narrow slits of widths comparable to the London penetration depth (≂0.15 μm). The design allows us to decrease the geometric size of the RSFQ cell. Test circuits with YBaCuO grain boundary junctions on asymmetric 32° Y– ZrO2 bicrystals were used to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 μm slit was found to be 0.7–0.8 pH/μm.
InductEx [1] is a software tool used for the analysis of integrated circuit designs and extraction of design parameters by way of numerical electromagnetic field solving. This tool was originally developed with Rapid Single Flux Quantum (RSFQ) chips in mind, but it has a broad applicability and can be extended to other processes. In this poster, we report a comprehensive analysis of a superconducting aluminum two qubit chip. This analysis was performed with InductEx. We report the design of a two qubit chip which has the characteristics necessary to execute single and two qubit gates. Ahead of fabrication, several design characteristics have been extracted from this quantum chip design in order to verify that it satisfies basic design principles of transmon qubits. These characteristics are reported in this poster and they include the calculation of chip anharmonicities, qubit frequencies, resonator frequencies as well as g-factors and dispersive shifts. Design constraints which are satisfied by these extracted parameters are discussed. Additionally, qualitative aspects of the chip have been obtained from current density maps and are reported here. Taken as a whole, this analysis demonstrates the broad applicability of Inductex to integrated circuit design and particularly to the problem of quantum circuit layout optimization.
We suggest a new design of Rapid Single Flux Quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. The small inductances of about 10 pH, that are obligatory for the RSFQ applications, are formed as narrow slits with width comparable to the London penetration depth (/spl cong/0.15 /spl mu/m). The design allows us to decrease the geometric size of the RSFQ cell and can be applied to low-T/sub c/ circuits as well. Test circuits have been implemented using YBaCuO grain boundary junctions on assymmetric 32/spl deg/Y-ZrO/sub 2/ bi-crystals to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 pm slit was determined to be 0.7pH//spl mu/m. We present a new design and a computer simulation of a flip-flop circuit based on these inductance measurements. To realize these circuits experimentally one needs at least two grain boundaries, separated by a distance of 10 to l5 /spl mu/m, or to use bi-epitaxial or step-edge junction technology.>
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
The MIT Lincoln Lab SFQ4ee and SFQ5ee process nodes, targeted at energy-efficient superconducting digital circuits, allow the fabrication of complicated multilayer circuit structures. Published per-length inductance values do not hold if ground plane (GP) and sky plane (SP) combinations are changed, or if inductance is distributed over multiple via-connected layers with current return paths determined by the specific placement of sky-to-ground vias. A three-dimensional inductance extraction tool, InductEx, can handle extraction from such complicated multilayer structures with holes in the GPs and SPs. We present calibrated parameter sets for InductEx generated from the analysis of twelve representative test structures. We show that the root-mean-squared-error (RMSE) between InductEx extractions and averaged experimental measurements of self-inductance are below 1% for several calibration sets-The lowest ever reported. The RMSE between calculations and measurements for mutual inductance is also below 1% for the best calibration set-A level also never achieved before.