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Applied Physics Letters

Novel design of rapid single flux quantum logic based on a single layer of a high-T c superconductor

V. K. Kaplunenko, Z. G. Ivanov, Е. А. Степанцов, T. Claeson, Thorsten Holst, Zechen Sun, R. Kromann, Y.Q. Shen, Per Vase, Torsten Freltoft, E. Wikborg

Published Jul 3, 1995• 23 citations
Publisher

Abstract

We suggest a new design of rapid single flux quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. Small inductances of about 10 pH, obligatory for RSFQ circuits, are formed as narrow slits of widths comparable to the London penetration depth (≂0.15 μm). The design allows us to decrease the geometric size of the RSFQ cell. Test circuits with YBaCuO grain boundary junctions on asymmetric 32° Y– ZrO2 bicrystals were used to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 μm slit was found to be 0.7–0.8 pH/μm.

DOI
10.1063/1.115472

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Journal of Applied Physics•Oct 3, 2003•130 citations
We suggest a new design of rapid single flux quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. Small inductances of about 10 pH, obligatory for RSFQ circuits, are formed as narrow slits of widths comparable to the London penetration depth (≂0.15 μm). The design allows us to decrease the geometric size of the RSFQ cell. Test circuits with YBaCuO grain boundary junctions on asymmetric 32° Y– ZrO2 bicrystals were used to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 μm slit was found to be 0.7–0.8 pH/μm.
We suggest a new design of Rapid Single Flux Quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. The small inductances of about 10 pH, that are obligatory for the RSFQ applications, are formed as narrow slits with width comparable to the London penetration depth (/spl cong/0.15 /spl mu/m). The design allows us to decrease the geometric size of the RSFQ cell and can be applied to low-T/sub c/ circuits as well. Test circuits have been implemented using YBaCuO grain boundary junctions on assymmetric 32/spl deg/Y-ZrO/sub 2/ bi-crystals to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 pm slit was determined to be 0.7pH//spl mu/m. We present a new design and a computer simulation of a flip-flop circuit based on these inductance measurements. To realize these circuits experimentally one needs at least two grain boundaries, separated by a distance of 10 to l5 /spl mu/m, or to use bi-epitaxial or step-edge junction technology.>
Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>
A simple test circuit of the rapid single-flux-quantum (RSFQ) logic family has been implemented in a planarized all-refractory technology using only two superconducting layers and small Nb/AlOx/Nb Josephson junctions (nominally 1.5×1.5 μm2) with critical current density jc≊6 kA/cm2. A special layout design of the integrated circuit (including a SFQ pulse generator, Josephson transmission line, and T flip–flop) was used to reduce 3D inductances resulting from absence of the ground plane. For samples with various junction parameters, the maximum frequency of the SFQ pulse train, which could be divided by 2 by the flip–flop, ranged from 200 to 370 GHz.
We have designed, fabricated and successfully tested three SFQ elements: a toggle flip-flop, a SFQ voltage amplifier, and an RS-flip-flop. The design uses a single superconducting layer and it is optimized by repeated computer simulations and repeated inductance calculations. The inductances are made as narrow slits of 0.5 /spl mu/m width. Their values are calculated numerically taking into account material parameters derived from experiment. The YBCO junctions are either of step edge type on LaAlO/sub 3/ substrates or located on two closely spaced bi-crystal grain boundaries on a novel YSZ tricrystal substrate. Carbon masks were used to form steps on LaAlO/sub 3/ substrates and for the YBCO patterning. Voltage amplifier shows operation up to 60 K, and both flip-flops were observed to operate at temperatures up to 30 K with parameters close to the simulated values. The operation frequency of a T-flip-flop cell of about 150 GHz was achieved and a new measurement technique of the margins of an RS trigger is suggested.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.
We have found that the size of some rapid single-flux quantum (RSFQ) logic cells based on conventional 0-type Josephson junctions can be significantly reduced by using a π-type junction as a phase shifter in passive (nonswitching) mode. In comparison with the recently suggested active (switching) π-junctions mode, the passive mode offers much greater operation margins for their critical current Icπ. This gives π-junctions a chance to be implemented in RSFQ designs in the near future. As an example, we have simulated the operation of a toggle flip flop with zero-geometrical inductance of the fluxon storage loop. Simulations show that the parametric inductance of the π-junction and its normal resistance Rn form a low-pass filter, which sets the low limit for π-junctions IcπRn product, but offers a wide range of variations of the other parameters. The possible reduction of RSFQ cell size by using π-junctions opens the way to scale superconducting logic circuits down to the submicron dimensions.