InductEx [1] is a software tool used for the analysis of integrated circuit designs and extraction of design parameters by way of numerical electromagnetic field solving. This tool was originally developed with Rapid Single Flux Quantum (RSFQ) chips in mind, but it has a broad applicability and can be extended to other processes. In this poster, we report a comprehensive analysis of a superconducting aluminum two qubit chip. This analysis was performed with InductEx. We report the design of a two qubit chip which has the characteristics necessary to execute single and two qubit gates. Ahead of fabrication, several design characteristics have been extracted from this quantum chip design in order to verify that it satisfies basic design principles of transmon qubits. These characteristics are reported in this poster and they include the calculation of chip anharmonicities, qubit frequencies, resonator frequencies as well as g-factors and dispersive shifts. Design constraints which are satisfied by these extracted parameters are discussed. Additionally, qualitative aspects of the chip have been obtained from current density maps and are reported here. Taken as a whole, this analysis demonstrates the broad applicability of Inductex to integrated circuit design and particularly to the problem of quantum circuit layout optimization.
InductEx [1] is a software tool used for the analysis of integrated circuit designs and extraction of design parameters by way of numerical electromagnetic field solving. This tool was originally developed with Rapid Single Flux Quantum (RSFQ) chips in mind, but it has a broad applicability and can be extended to other processes. In this poster, we report a comprehensive analysis of a superconducting aluminum two qubit chip. This analysis was performed with InductEx. We report the design of a two qubit chip which has the characteristics necessary to execute single and two qubit gates. Ahead of fabrication, several design characteristics have been extracted from this quantum chip design in order to verify that it satisfies basic design principles of transmon qubits. These characteristics are reported in this poster and they include the calculation of chip anharmonicities, qubit frequencies, resonator frequencies as well as g-factors and dispersive shifts. Design constraints which are satisfied by these extracted parameters are discussed. Additionally, qualitative aspects of the chip have been obtained from current density maps and are reported here. Taken as a whole, this analysis demonstrates the broad applicability of Inductex to integrated circuit design and particularly to the problem of quantum circuit layout optimization.
The design of single flux-quantum (SFQ) circuits requires well-defined inductances. In many cases these are created by irregular geometries and a computer-aided design tool is necessary for inductance calculations. This becomes a challenging task in cases where no ground plane is used and thus three-dimensional calculations are required. For this purpose, InductEx was developed and verified successfully for simple structures. In this work we take the next step and demonstrate the applicability of InductEx to the design of rapid single flux-quantum (RSFQ) cells. We use InductEx for inductance modeling as an integral part of the design cycle for an RSFQ cell with flux quantum transfer via mutual inductance and for a DC-reprogrammable logic circuit with similar inductive coupling. The relation between coupling factor and self-inductance is optimized in the circuit layout. All coupling structures are duplicated in SQUID modulation test circuits to measure and verify calculation accuracy. We find excellent agreement between the calculated and measured inductance values. Furthermore, the operational area of the basic cell is determined and compared with similar investigations reported earlier. Based on this comparison we conclude that InductEx is a valuable inductance design tool, and that mutual coupling in structures using ground plane holes and RSFQ-compatible self-inductances can be modeled and designed reliably.
At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.
This work presents a comprehensive analytical and simulation-based study of superconducting quantum chip architectures, spanning both 2D planar and 3D-integrated designs. We first design and simulate a planar quantum chip layout using Qiskit Metal, which is imported into Ansys HFSS (High Frequency Structure Simulator) to construct a 3D model and perform electromagnetic simulations. A detailed analysis using Driven Modal, Eigenmode, Magnetostatic, and Q3D Capacitance Extraction solvers ensures our simulations accurately reflect physical behavior. The results are validated against analytical models from microwave engineering. pyEPR (Python Energy Participation Ratio) is used to extract key quantum metrics, including eigenfrequencies, quality factors, decoherence times, anharmonicity, cross-Kerr interactions, and participation ratios. Building on this planar design, we extend our study to a 3D-integrated flip-chip architecture featuring two superconducting qubits fabricated on separate high-resistivity silicon substrates. Using HFSS and analytical modeling, we show that detuned qubits maintain stable eigenfrequencies, quality factors, decoherence times, anharmonicity, and cross-Kerr interactions over varying substrate separation values. However, the introduction of dielectric loss tangents reduces quality factors which degrades coherence times and introduces an additional dephasing. These findings highlight the potential of 3D quantum integration, given minimal material imperfections.The planar and 3D designs together form a cohesive investigation into next-generation quantum hardware, with the 2D layout currently taped-out and under fabrication.
Abstract To meet the specification of the qubits in our laboratory, a 0.4 kA·cm −2 superconducting rapid single flux quantum (RSFQ) circuit was designed and successfully fabricated with an improved Nb‐based self‐aligned lift‐off process. This circuit consists of a single‐flux‐quantum (SFQ) pulse generator, a Josephson transmission line (JTL) and a T‐flip flop (TFF), and it acts as a frequency divider. The values of the inductors in this circuit were extracted using InductEX and the basic function of this circuit was confirmed using the simulation software WRspice before fabrication. After fabrication, the basic parameters of this circuit were measured at ~ 2.5 K in a Janis He‐3 cryostat. This work laid the theoretical and experimental basis for the future research on the RSFQ‐qubit control circuits.
In the design of superconducting quantum chips, the control and readout of the quantum bit (qubit) are realized through interactions with other components in the circuit, such as drive lines, flux lines and readout resonator. Depending on the design, these interactions employ either an inductive or capacitive coupling scheme. Note that every interaction governs critical performance metrics for the chip, including gate fidelity, readout speed, and coherence times, a more effective and precise approach to extract the strength of the coupling is necessary. For most qubit designs, the structure of the qubit typically remains in the electrically small regime. Therefore, simulation software based on static fields and the Method of Moments (MoM), such as Q3D, is still applicable in most instances. However, as the number of qubits on a chip increases, Q3D faces challenges in effectively addressing the complex coupling and crosstalk issues present on the chip. In this work, we extend the lumped-element-based qubit model by using microwave network parameters and thus enable the simulation of the qubit for the Finite Element Method (FEM)-based 3D electromagnetic simulation software, such as HFSS. This approach is suitable for the determination of the capacitive coupling strength between the qubit and the drive line, as well as readout circuits. Furthermore, to address the inductive coupling between the qubit and the flux line, we propose a method in this work that directly computes the mutual inductance, which is implemented by determining the magnetic flux through the DC SQUID area, generated by the current port excitation in HFSS. The proposed methodologies not only effectively extracts the key qubit design parameters, but also offer broader applicability for analysing complex crosstalk in multi-qubit chip designs.
Quantum computing is advancing rapidly, with superconducting quantum computing (SQC) emerging as one of the most promising platforms for scalable quantum information processing. In contrast to fabrication-focused approaches prevalent in current literature, this work presents a fully simulation-based design and tuning methodology for a small-scale superconducting quantum chip - addressing practical limitations posed by fabrication resource constraints - and consequently excludes physical chip fabrication or real-time performance evaluation (e.g., fidelity and error rate measurements). A meticulous, step-by-step electromagnetic simulation was conducted on the chip, designed using Qiskit Metal and Ansys Electronics, with qubit parameters tuned and verified using the Lumped Oscillator Model (LOM) and Energy Participation Ratio (EPR) methods. The design achieves good parameter convergence with relative tuning error rates (Δ%) below 0.05% after 15 adaptive passes and approximately 50,000 solved mesh elements, yielding an Energy Participation Ratio (EPR) of 91.8 % for the chip substrate (Silicon). Furthermore, the study includes a theoretical comparison between two fundamental qubit-qubit coupling schemes. A key contribution of this work lies in systematically analyzing how geometric variations in qubit design affect critical quantum parameters such as qubit frequencies, anharmonicities, coupling strengths, and dispersive shifts - thereby offering a comprehen-sive, simulation-driven framework for early-stage quantum chip prototyping.