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IEEE Transactions on Applied Superconductivity

Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx

Coenrad Johann Fourie

Published Sep 30, 2014• 56 citations
Publisher

Abstract

At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.

DOI
10.1109/tasc.2014.2360870

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At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.
The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.
Abstract Currently, fabrication processes for superconductive integrated circuits are moving to multiple wiring and shielding layers, some of which are placed below the main ground plane (GP) and device layers. The Advanced Industrial Science and Technology advanced process (ADP2) was the first such multi-layer Nb process with planarized passive transmission line and GP layers below the junction layer, and is at the time of writing still the most developed. This process allows complex circuit designs, and accurate inductance extraction helps to push the boundaries of the layouts possible. We show that the position of ground connections between ground layers influences the inductance of structures for which these GPs act as return path, and that this needs to be accounted for in modelling. However, due to the number of wiring layers and GPs, full layout modelling of large cells causes long calculation times. In this paper we discuss methods with which to reduce model size, and calibrate InductEx calculations using these methods against measured results. We show that model reduction followed by calibration results in fast calculation times while good accuracy is maintained. We also show that InductEx correctly handles coupling between conductors in a multi-layer layout, and how to model layouts to gauge unwanted coupling between power lines and single flux quantum electronics.
InductEx [1] is a software tool used for the analysis of integrated circuit designs and extraction of design parameters by way of numerical electromagnetic field solving. This tool was originally developed with Rapid Single Flux Quantum (RSFQ) chips in mind, but it has a broad applicability and can be extended to other processes. In this poster, we report a comprehensive analysis of a superconducting aluminum two qubit chip. This analysis was performed with InductEx. We report the design of a two qubit chip which has the characteristics necessary to execute single and two qubit gates. Ahead of fabrication, several design characteristics have been extracted from this quantum chip design in order to verify that it satisfies basic design principles of transmon qubits. These characteristics are reported in this poster and they include the calculation of chip anharmonicities, qubit frequencies, resonator frequencies as well as g-factors and dispersive shifts. Design constraints which are satisfied by these extracted parameters are discussed. Additionally, qualitative aspects of the chip have been obtained from current density maps and are reported here. Taken as a whole, this analysis demonstrates the broad applicability of Inductex to integrated circuit design and particularly to the problem of quantum circuit layout optimization.
New tools have been created to allow a superconducting design flow for schematic design, verification, and optimization. These tools integrate with the Cadence design environment. In single flux quantum superconducting electronics, individual component values, such as wire inductances, Josephson junction critical currents, and bias currents, must be optimized to allow for maximum deviance from the designer value, which is also known as the device margin. One tool is used to create a description of the proper circuit behavior. Included with this tool is the ability to automatically create the description from a Cadence netlist. The other tool is an automated device margin circuit schematic verification and optimization tool, which widens device margins while maintaining proper circuit behavior derived from the first tool. Additionally, this optimization tool can automatically correct the circuit schematic using the proper circuit behavior description. In this paper, the functionality of the language used to create the description of the proper circuit behavior is presented. Several circuits are then verified and optimized based on their correct behavior.
The MIT Lincoln Lab SFQ4ee and SFQ5ee process nodes, targeted at energy-efficient superconducting digital circuits, allow the fabrication of complicated multilayer circuit structures. Published per-length inductance values do not hold if ground plane (GP) and sky plane (SP) combinations are changed, or if inductance is distributed over multiple via-connected layers with current return paths determined by the specific placement of sky-to-ground vias. A three-dimensional inductance extraction tool, InductEx, can handle extraction from such complicated multilayer structures with holes in the GPs and SPs. We present calibrated parameter sets for InductEx generated from the analysis of twelve representative test structures. We show that the root-mean-squared-error (RMSE) between InductEx extractions and averaged experimental measurements of self-inductance are below 1% for several calibration sets-The lowest ever reported. The RMSE between calculations and measurements for mutual inductance is also below 1% for the best calibration set-A level also never achieved before.
The design of single flux-quantum (SFQ) circuits requires well-defined inductances. In many cases these are created by irregular geometries and a computer-aided design tool is necessary for inductance calculations. This becomes a challenging task in cases where no ground plane is used and thus three-dimensional calculations are required. For this purpose, InductEx was developed and verified successfully for simple structures. In this work we take the next step and demonstrate the applicability of InductEx to the design of rapid single flux-quantum (RSFQ) cells. We use InductEx for inductance modeling as an integral part of the design cycle for an RSFQ cell with flux quantum transfer via mutual inductance and for a DC-reprogrammable logic circuit with similar inductive coupling. The relation between coupling factor and self-inductance is optimized in the circuit layout. All coupling structures are duplicated in SQUID modulation test circuits to measure and verify calculation accuracy. We find excellent agreement between the calculated and measured inductance values. Furthermore, the operational area of the basic cell is determined and compared with similar investigations reported earlier. Based on this comparison we conclude that InductEx is a valuable inductance design tool, and that mutual coupling in structures using ground plane holes and RSFQ-compatible self-inductances can be modeled and designed reliably.