Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Superconductor Science and Technology

Fast and accurate inductance and coupling calculation for a multi-layer Nb process

Coenrad Johann Fourie, Akitomo Takahashi, Nobuyuki Yoshikawa

Published Feb 2, 2015• 12 citations
Publisher

Abstract

Abstract Currently, fabrication processes for superconductive integrated circuits are moving to multiple wiring and shielding layers, some of which are placed below the main ground plane (GP) and device layers. The Advanced Industrial Science and Technology advanced process (ADP2) was the first such multi-layer Nb process with planarized passive transmission line and GP layers below the junction layer, and is at the time of writing still the most developed. This process allows complex circuit designs, and accurate inductance extraction helps to push the boundaries of the layouts possible. We show that the position of ground connections between ground layers influences the inductance of structures for which these GPs act as return path, and that this needs to be accounted for in modelling. However, due to the number of wiring layers and GPs, full layout modelling of large cells causes long calculation times. In this paper we discuss methods with which to reduce model size, and calibrate InductEx calculations using these methods against measured results. We show that model reduction followed by calibration results in fast calculation times while good accuracy is maintained. We also show that InductEx correctly handles coupling between conductors in a multi-layer layout, and how to model layouts to gauge unwanted coupling between power lines and single flux quantum electronics.

DOI
10.1088/0953-2048/28/3/035013

Related papers

High-Accuracy InductEx Calibration Sets for MIT-LL SFQ4ee and SFQ5ee Processes

Coenrad Johann Fourie, Claudio Shawawreh, I. V. Vernik +1 more

The MIT Lincoln Lab SFQ4ee and SFQ5ee process nodes, targeted at energy-efficient superconducting digital circuits, allow the fabrication of complicated multilayer circuit structures. Published per-length inductance values do not hold if ground plane (GP) and sky plane (SP) combinations are changed, or if inductance is distributed over multiple via-connected layers with current return paths determined by the specific placement of sky-to-ground vias. A three-dimensional inductance extraction tool, InductEx, can handle extraction from such complicated multilayer structures with holes in the GPs and SPs. We present calibrated parameter sets for InductEx generated from the analysis of twelve representative test structures. We show that the root-mean-squared-error (RMSE) between InductEx extractions and averaged experimental measurements of self-inductance are below 1% for several calibration sets-The lowest ever reported. The RMSE between calculations and measurements for mutual inductance is also below 1% for the best calibration set-A level also never achieved before.

IEEE Transactions on Applied Superconductivity•Jan 24, 2017•28 citations

Planarization Process for Fabricating Multi-Layer Nb Integrated Circuits Incorporating Top Active Layer

T. Satoh, K. Hinode, Shuichi Nagasawa +7 more

We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

IEEE Transactions on Applied Superconductivity•Jun 1, 2009•16 citations

Fabrication Process of Planarized Multi-Layer Nb Integrated Circuits

T. Satoh, K. Hinode, Hiroyuki Akaike +3 more

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

IEEE Transactions on Applied Superconductivity•Jun 1, 2005•42 citations

Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx

Coenrad Johann Fourie

At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.

IEEE Transactions on Applied Superconductivity•Sep 30, 2014•56 citations

Layout Strategies for Connecting Multiple Superconducting Ground Planes with Ground Pillars

Kyle Jackman, Coenrad Johann Fourie

Several advances have been made towards increasing the number of Niobium layers for superconductor integrated circuits. Fabrication processes, such as the MIT Lincoln Laboratory SFQ5ee process and the CRAVITY-AIST process, now provide eight or more Niobium layers. The additional superconducting layers significantly increase the space available for routing between and within cells. However, striplines must now be routed through multiple ground planes to efficiently utilize all available metal layers. This can lead to large mutual inductance between signal lines, especially when ground pillars are used to connect ground planes. The placement of these ground pillars become crucial. In this work, we use numerical software to analyze the effects of striplines transitioning through multiple ground planes and how the location of ground pillars influence the mutual inductance between lines and show that careful layout considerations are required for modern circuits with dense layouts. We also present layout improvement strategies to mitigate or lessen the negative effects of these mutual inductance on circuit operation.

IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2019•0 citations

Inductance of superconductor integrated circuit features with sizes down to 120 nm

Sergey K. Tolpygo, Evan B. Golden, Terence J. Weir +1 more

Abstract Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.

arXiv:2101.07457•Superconductor Science and Technology•May 25, 2021•47 citations
Abstract Currently, fabrication processes for superconductive integrated circuits are moving to multiple wiring and shielding layers, some of which are placed below the main ground plane (GP) and device layers. The Advanced Industrial Science and Technology advanced process (ADP2) was the first such multi-layer Nb process with planarized passive transmission line and GP layers below the junction layer, and is at the time of writing still the most developed. This process allows complex circuit designs, and accurate inductance extraction helps to push the boundaries of the layouts possible. We show that the position of ground connections between ground layers influences the inductance of structures for which these GPs act as return path, and that this needs to be accounted for in modelling. However, due to the number of wiring layers and GPs, full layout modelling of large cells causes long calculation times. In this paper we discuss methods with which to reduce model size, and calibrate InductEx calculations using these methods against measured results. We show that model reduction followed by calibration results in fast calculation times while good accuracy is maintained. We also show that InductEx correctly handles coupling between conductors in a multi-layer layout, and how to model layouts to gauge unwanted coupling between power lines and single flux quantum electronics.
The MIT Lincoln Lab SFQ4ee and SFQ5ee process nodes, targeted at energy-efficient superconducting digital circuits, allow the fabrication of complicated multilayer circuit structures. Published per-length inductance values do not hold if ground plane (GP) and sky plane (SP) combinations are changed, or if inductance is distributed over multiple via-connected layers with current return paths determined by the specific placement of sky-to-ground vias. A three-dimensional inductance extraction tool, InductEx, can handle extraction from such complicated multilayer structures with holes in the GPs and SPs. We present calibrated parameter sets for InductEx generated from the analysis of twelve representative test structures. We show that the root-mean-squared-error (RMSE) between InductEx extractions and averaged experimental measurements of self-inductance are below 1% for several calibration sets-The lowest ever reported. The RMSE between calculations and measurements for mutual inductance is also below 1% for the best calibration set-A level also never achieved before.
We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.
To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.
At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.
Several advances have been made towards increasing the number of Niobium layers for superconductor integrated circuits. Fabrication processes, such as the MIT Lincoln Laboratory SFQ5ee process and the CRAVITY-AIST process, now provide eight or more Niobium layers. The additional superconducting layers significantly increase the space available for routing between and within cells. However, striplines must now be routed through multiple ground planes to efficiently utilize all available metal layers. This can lead to large mutual inductance between signal lines, especially when ground pillars are used to connect ground planes. The placement of these ground pillars become crucial. In this work, we use numerical software to analyze the effects of striplines transitioning through multiple ground planes and how the location of ground pillars influence the mutual inductance between lines and show that careful layout considerations are required for modern circuits with dense layouts. We also present layout improvement strategies to mitigate or lessen the negative effects of these mutual inductance on circuit operation.
Abstract Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.