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IEEE International Superconductive Electronics Conference (ISEC)

Layout Strategies for Connecting Multiple Superconducting Ground Planes with Ground Pillars

Kyle Jackman, Coenrad Johann Fourie

Published Jul 1, 2019• 0 citations
Publisher

Abstract

Several advances have been made towards increasing the number of Niobium layers for superconductor integrated circuits. Fabrication processes, such as the MIT Lincoln Laboratory SFQ5ee process and the CRAVITY-AIST process, now provide eight or more Niobium layers. The additional superconducting layers significantly increase the space available for routing between and within cells. However, striplines must now be routed through multiple ground planes to efficiently utilize all available metal layers. This can lead to large mutual inductance between signal lines, especially when ground pillars are used to connect ground planes. The placement of these ground pillars become crucial. In this work, we use numerical software to analyze the effects of striplines transitioning through multiple ground planes and how the location of ground pillars influence the mutual inductance between lines and show that careful layout considerations are required for modern circuits with dense layouts. We also present layout improvement strategies to mitigate or lessen the negative effects of these mutual inductance on circuit operation.

DOI
10.1109/isec46533.2019.8990963

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Several advances have been made towards increasing the number of Niobium layers for superconductor integrated circuits. Fabrication processes, such as the MIT Lincoln Laboratory SFQ5ee process and the CRAVITY-AIST process, now provide eight or more Niobium layers. The additional superconducting layers significantly increase the space available for routing between and within cells. However, striplines must now be routed through multiple ground planes to efficiently utilize all available metal layers. This can lead to large mutual inductance between signal lines, especially when ground pillars are used to connect ground planes. The placement of these ground pillars become crucial. In this work, we use numerical software to analyze the effects of striplines transitioning through multiple ground planes and how the location of ground pillars influence the mutual inductance between lines and show that careful layout considerations are required for modern circuits with dense layouts. We also present layout improvement strategies to mitigate or lessen the negative effects of these mutual inductance on circuit operation.
Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths from 250 nm to a few micrometers, located on the same layer at various distances from each other, from 250 nm to a few micrometers, and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; and inductance of meanders. Measurements were done using circuits fabricated in the SFQ5ee and the SC1 fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, developed at MIT Lincoln Laboratory for superconductor electronics. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% over a very wide range of parameters. Mutual coupling between microstrips is long-ranged and decreases as a second power of distance between them, making microstrips unsuitable for very large scale integrated circuits. Mutual inductance of striplines decreases exponentially with distance between them on a scale of(H+2λ)/π({\boldsymbol{H}} + 2{\boldsymbol{\lambda }})/{\boldsymbol{\pi }}(H+2λ)/π∼ 0.3 μm, whereH{\boldsymbol{H}}Handλ{\boldsymbol{\lambda }}λare, respectively, the distance between and magnetic field penetration depth in superconducting ground planes, whereas superconducting properties of the signal traces are practically irrelevant. This decay distance determines the scale of integration above which adjacent inductors in a circuit become strongly coupled. Dependence of mutual inductance on the linewidth of wires is weak. As a result, the area of flux transformers—an essential component of all superconductor digital circuits using ac power, qubits, and sensor arrays—scales poorly with the linewidth, potentially restricting scalability of the circuits.
We present measurements of the self- and mutual inductance of NbN and NbN/Nb bilayer inductors (microstrips, striplines, serpentines, etc.) with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with${{\bm{T}}}_{\bm{c}} \approx 15.5Koranin−situdepositedNbN/Nbbilayer,replacinga200−nmNblayerM6inthestandardSFQ5eeprocesswithninesuperconductinglayerson200−mmwafers.Nbgroundplanesarepreservedtomaintainahighlevelofinterlayershieldingandlowintralayermutualcoupling.Atwo−steppatterningofthetopNbandthebottomNbNlayersoftheNbN/Nbbilayerallowsthecreationofinductorswithaverywiderangeofinductances,fromlowvalues∼0.4pH/μmtypicalforNbgeometricalinductorsto∼35pH/μmtypicalforthin−filmkineticinductors.ThemutualinductanceofvariouscombinationsofNbN,Nb,andNbN/Nbinductorsdoesnotdependonsuperconductingpropertiesofthesignaltracesinthestudiedrangeoflinewidths,15.5 K or an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers on 200-mm wafers. Nb ground planes are preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows the creation of inductors with a very wide range of inductances, from low values ∼0.4 pH/μm typical for Nb geometrical inductors to ∼35 pH/μm typical for thin-film kinetic inductors. The mutual inductance of various combinations of NbN, Nb, and NbN/Nb inductors does not depend on superconducting properties of the signal traces in the studied range of linewidths,15.5Koranin−situdepositedNbN/Nbbilayer,replacinga200−nmNblayerM6inthestandardSFQ5eeprocesswithninesuperconductinglayerson200−mmwafers.Nbgroundplanesarepreservedtomaintainahighlevelofinterlayershieldingandlowintralayermutualcoupling.Atwo−steppatterningofthetopNbandthebottomNbNlayersoftheNbN/Nbbilayerallowsthecreationofinductorswithaverywiderangeofinductances,fromlowvalues∼0.4pH/μmtypicalforNbgeometricalinductorsto∼35pH/μmtypicalforthin−filmkineticinductors.ThemutualinductanceofvariouscombinationsofNbN,Nb,andNbN/Nbinductorsdoesnotdependonsuperconductingpropertiesofthesignaltracesinthestudiedrangeoflinewidths,{\bm{w}};itequalsthemutualinductanceoftheNbinductorswiththeequivalentgeometryandplacementbetweenthegroundplanes.ThemeasuredmagneticfieldpenetrationdepthinNbNfilmsdepositedbyreactivesputteringat200°CisλNbN=491±5nm.Themeasuredkineticinductanceofthefilmswiththicknesses; it equals the mutual inductance of the Nb inductors with the equivalent geometry and placement between the ground planes. The measured magnetic field penetration depth in NbN films deposited by reactive sputtering at 200 °C isλNbN= 491 ± 5 nm. The measured kinetic inductance of the films with thicknesses;itequalsthemutualinductanceoftheNbinductorswiththeequivalentgeometryandplacementbetweenthegroundplanes.ThemeasuredmagneticfieldpenetrationdepthinNbNfilmsdepositedbyreactivesputteringat200°CisλNbN=491±5nm.Themeasuredkineticinductanceofthefilmswiththicknesses{\bm{t}}\ = {\bm{\ }}200nmand150nm,respectively1.51pH/sqand2.06pH/sq,islargerthanthatexpectedforconventionalsuperconductorswithshortmeanfreepath,correspondingtoabout25200 nm and 150 nm, respectively 1.51 pH/sq and 2.06 pH/sq, is larger than that expected for conventional superconductors with short mean free path, corresponding to about 25% lower superfluid density. We also measured kinetic inductance of the right-angle bends of NbN striplines and found it to be negligible at200nmand150nm,respectively1.51pH/sqand2.06pH/sq,islargerthanthatexpectedforconventionalsuperconductorswithshortmeanfreepath,correspondingtoabout25{\bm{w}} < {\bm{\lambda }}_{{\bm{NbN}}}^2/{\bm{t}}$, indicating an insignificant effect of current crowding in the presence of superconducting ground plane(s). Implementing NbN and NbN/Nb kinetic inductors enables a significant increase in the integration scale of superconductor digital electronics.
Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90° bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities> 106Josephson junctions per cm2are discussed.
Abstract Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant superconducting layers. Test circuits used for the measurements were fabricated in a new 150 nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laboratory for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193 nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using software packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.
Magnetic isolation is an important issue in the realization of superconducting LSIs including more than ten thousands Josephson junctions. In this paper, we present mutual inductances of two superconducting strip lines coupled through a grounded shield layer. A conventional dc-superconducting quantum interference device (dc-SQUID) method on Nb/AlO x /Nb Josephson IC chips is employed. We have tested one dc-SQUID layout with a floating shield layer for reference, and ten dc-SQUID layouts with grounded shield layers. Four superconducting niobium layers are used as a ground plane, a SQUID line, a shield layer, and a control line from bottom to top. We have confirmed that the number, positions, and dimensions of ground contacts make differences in the mutual inductances. Ground contacts should be placed to enhance the shielding current for effective magnetic isolation.
Abstract Currently, fabrication processes for superconductive integrated circuits are moving to multiple wiring and shielding layers, some of which are placed below the main ground plane (GP) and device layers. The Advanced Industrial Science and Technology advanced process (ADP2) was the first such multi-layer Nb process with planarized passive transmission line and GP layers below the junction layer, and is at the time of writing still the most developed. This process allows complex circuit designs, and accurate inductance extraction helps to push the boundaries of the layouts possible. We show that the position of ground connections between ground layers influences the inductance of structures for which these GPs act as return path, and that this needs to be accounted for in modelling. However, due to the number of wiring layers and GPs, full layout modelling of large cells causes long calculation times. In this paper we discuss methods with which to reduce model size, and calibrate InductEx calculations using these methods against measured results. We show that model reduction followed by calibration results in fast calculation times while good accuracy is maintained. We also show that InductEx correctly handles coupling between conductors in a multi-layer layout, and how to model layouts to gauge unwanted coupling between power lines and single flux quantum electronics.