The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.
The IARPA SuperTools program has accelerated the development of superconductor integrated circuit design tools. Superconductor integrated circuits contain Josephson junctions and rely heavily on inductive interconnects and coupled inductors, all of which are not adequately supported by conventional semiconductor layout-versus-schematic verification (LVS) tools. Such circuits are also susceptible to failure in the presence of magnetic fields above about one tenth of the Earth's field strength and to magnetic flux trapped in layout structures during cool-down, so that magnetic rule checking (MRC) is essential. Under SuperTools we developed an open-source LVS framework, SPiRA, which allows for the parametric creation, alteration and verification of superconductor and quantum circuit layouts. SPiRA is a Python-based framework developed to aid the process of creating parameterized layouts while simultaneously taking into account design rule (DRC) as well as magnetic rule checking. SPiRA is designed to accept any process through a rule deck database (RDD) Python-based PDK schema from which cells are spawned as objects with inherent properties. This process allows rapid implementation of changes to layouts with the ability to extract an electrical netlist that can be simulated, and parameter extraction performed upon. SPiRA creates layouts in the GDSII layout format and allows quick visualization of the layout using the Gdspy library. We present extraction results for examples created parametrically with SPiRA, compare those to results for layouts created by hand and evaluate the capabilities of SPiRA. Finally we show how SPiRA improves models for inductance and compact model extraction with the inductance extraction tool InductEx.
At present, superconducting integrated circuit layouts are verified through a variety of techniques. A layout-versus-schematic method implemented in Cadence allows extraction of circuit schematics with certain geometry-dependent parameters. Lmeter calculates inductance in a layout network and, with proper setup, may also calculate resistance separately. Recently, InductEx was introduced to calculate multiterminal network inductance in a superconductor structure with support for more complicated 3-D geometries. Here, we present an improvement to InductEx that allows resistance, inductance, and Josephson junction critical current extraction of a full superconducting digital logic gate or cell in a single execution, as well as in reasonable time. We show how InductEx was designed to operate on tape-out ready layouts and, through example, how it is used for full-gate layout verification of contemporary logic cells.
In five and a half years, the ColdFlux project under the IARPA SuperTools program pushed the boundaries of digital and analog superconductor electronic design automation (S-EDA) tools. The SuperTools program demanded significant beyond-state-of-the-art deliverables in four main areas: RTL synthesis, architectures, and verification; analog design and layout synthesis; physical design and test; and technology CAD and cell library design. Through the work of academic groups scattered over four continents, the ColdFlux effort forged into a powerful set of open-source and commercial S-EDA tools unlike any before, rivaled only by a commercial toolchain from Synopsys under the same SuperTools umbrella. We present an overview of the tools from where we started to the eventual project deliverables. These include powerful simulation and extraction engines, magnetic field and flux trapping analysis, advanced clocking methods, multi-chip interface extraction and verification, unified multi-layer design-rule compliant track blocks for automated place and route of both rapid single flux quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cells, models and tools for validation and test, multi-bit single flux quantum (SFQ) cells, architecture innovations for full CPU designs and more. Comprehensive cell libraries and a process design kit (PDK) were developed with the ColdFlux tools. The AQFP cell library features a logically rich collection of 80+ cells, including 3- and 5-input logic gates, signal-driving boosters, and refined RSFQ-to-AQFP interfaces, while the RSFQ library has 30+ cells. Finally, we discuss how the full toolchain enables and enhances the superconductor IC design process.
Abstract Superconducting integrated circuits have long been completely handcrafted or at best designed with a loose collection of tools that require manual manipulation of data and design transfer between tools. Electronic Design Automation (EDA) software development requires significant investment of resources to track the evolution of integrated circuit fabrication processes, which has only been possible commercially for highly successful semiconductor integrated circuit processes. The IARPA SuperTools project which started in 2017 is the largest known investment to date made in superconducting EDA tool development. SuperTools is divided into two main categories: high-level tools for the synthesis of digital logic circuits, clock networks and placed-and-routed layouts for systems such as processors with millions of logic gates; and physical-level tools for the design, simulation, optimisation, verification, layout and parameter extraction of devices and digital logic cells with the inclusion of fabrication process simulation. In this paper the modules developed for the ColdFlux project under SuperTools are discussed from device modelling to chip tape-out. Progress on parameter extraction tools is highlighted.
The recent development of integrated Josephson circuits with increased complexity-e.g. RSFQ devices-invokes the need of a comprehensive computer-aided design support. The derivation of circuit parameters from layout data as well as an efficient and versatile simulation technique are essential means in the design and dimensioning of complex integrated structures. We present a comprehensive solution for calculating circuit parameters and simulating the device dynamics. The calculation of inductances and capacitances is performed by three-dimensional field computation using special developed programs which have been proven in high-T/sub c/ SQUID design. They can process layout information in standard graphic interchange formats (e.g. DXF). The netlists for device simulation can be generated automatically from the equivalent circuit schematic. Additionally, a technique for distributed simulation, which allows performing margins-and-yields-analyses in an efficient manner, was elaborated. The performance of the whole design tool set is demonstrated using basic RSFQ circuits.>
The semiconductor industry standard computer-aided-design (CAD) tool Cadence has been calibrated for a 3 /spl mu/m Niobium technology in order to design and build superconductive single flux quantum (SFQ) circuits. The top-down design methodology includes Verilog functional simulation, schematic capture, graphic layout, functional verification, design rule checking, electrical rule checking, and layout-vs.-schematic verification. This design framework has been used successfully at the University of Rochester in designing more than 15 elementary SFQ cells and three large scale digital and mixed-signal SFQ circuits, demonstrating significant improvement in both design efficiency and accuracy.
New tools have been created to allow a superconducting design flow for schematic design, verification, and optimization. These tools integrate with the Cadence design environment. In single flux quantum superconducting electronics, individual component values, such as wire inductances, Josephson junction critical currents, and bias currents, must be optimized to allow for maximum deviance from the designer value, which is also known as the device margin. One tool is used to create a description of the proper circuit behavior. Included with this tool is the ability to automatically create the description from a Cadence netlist. The other tool is an automated device margin circuit schematic verification and optimization tool, which widens device margins while maintaining proper circuit behavior derived from the first tool. Additionally, this optimization tool can automatically correct the circuit schematic using the proper circuit behavior description. In this paper, the functionality of the language used to create the description of the proper circuit behavior is presented. Several circuits are then verified and optimized based on their correct behavior.