Results From the ColdFlux Superconductor Integrated Circuit Design Tool Project
Coenrad Johann Fourie, Kyle Jackman, Johannes A. Delport, Lieze Schindler, Tessa Hall, Pascal Febvre, Lucas Iwanikow, Olivia Chen, Christopher Lawrence Ayala, Nobuyuki Yoshikawa, Mark E. Law, Thomas A. Weingartner, Yanzhi Wang, Peter A. Beerel, Sandeep K. Gupta, Haipeng Zha, Sasan Razmkhah, Mustafa Altay Karamuftuoglu, Arash Fayyazi, Mingye Li, Murali Annavaram, Shahin Nazarian, Massoud Pedram
In five and a half years, the ColdFlux project under the IARPA SuperTools program pushed the boundaries of digital and analog superconductor electronic design automation (S-EDA) tools. The SuperTools program demanded significant beyond-state-of-the-art deliverables in four main areas: RTL synthesis, architectures, and verification; analog design and layout synthesis; physical design and test; and technology CAD and cell library design. Through the work of academic groups scattered over four continents, the ColdFlux effort forged into a powerful set of open-source and commercial S-EDA tools unlike any before, rivaled only by a commercial toolchain from Synopsys under the same SuperTools umbrella. We present an overview of the tools from where we started to the eventual project deliverables. These include powerful simulation and extraction engines, magnetic field and flux trapping analysis, advanced clocking methods, multi-chip interface extraction and verification, unified multi-layer design-rule compliant track blocks for automated place and route of both rapid single flux quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cells, models and tools for validation and test, multi-bit single flux quantum (SFQ) cells, architecture innovations for full CPU designs and more. Comprehensive cell libraries and a process design kit (PDK) were developed with the ColdFlux tools. The AQFP cell library features a logically rich collection of 80+ cells, including 3- and 5-input logic gates, signal-driving boosters, and refined RSFQ-to-AQFP interfaces, while the RSFQ library has 30+ cells. Finally, we discuss how the full toolchain enables and enhances the superconductor IC design process.
In five and a half years, the ColdFlux project under the IARPA SuperTools program pushed the boundaries of digital and analog superconductor electronic design automation (S-EDA) tools. The SuperTools program demanded significant beyond-state-of-the-art deliverables in four main areas: RTL synthesis, architectures, and verification; analog design and layout synthesis; physical design and test; and technology CAD and cell library design. Through the work of academic groups scattered over four continents, the ColdFlux effort forged into a powerful set of open-source and commercial S-EDA tools unlike any before, rivaled only by a commercial toolchain from Synopsys under the same SuperTools umbrella. We present an overview of the tools from where we started to the eventual project deliverables. These include powerful simulation and extraction engines, magnetic field and flux trapping analysis, advanced clocking methods, multi-chip interface extraction and verification, unified multi-layer design-rule compliant track blocks for automated place and route of both rapid single flux quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cells, models and tools for validation and test, multi-bit single flux quantum (SFQ) cells, architecture innovations for full CPU designs and more. Comprehensive cell libraries and a process design kit (PDK) were developed with the ColdFlux tools. The AQFP cell library features a logically rich collection of 80+ cells, including 3- and 5-input logic gates, signal-driving boosters, and refined RSFQ-to-AQFP interfaces, while the RSFQ library has 30+ cells. Finally, we discuss how the full toolchain enables and enhances the superconductor IC design process.
The ColdFlux project, within the IARPA SuperTools program, aims to develop an open-source EDA tool suite for superconductor circuits, with focus on Rapid single flux quantum (RSFQ) and Adiabatic quantum-flux-parametron (AQFP) logic. The functionality of the ColdFlux tool suite is validated through the development of ready-to-use cell libraries. The process of establishing the open-source ColdFlux RSFQ cell library is documented, along with the set of EDA tools developed within the project required for each step. This includes the initial cell design using phase-based equations, circuit simulation, operating margin analysis, and cell parameter optimization. The row-based layout architecture for the RSFQ cell library is also presented. Several of the designed RSFQ cells are placed within test circuits and fabricated through the MIT-LL SFQ5ee fabrication process. We present the measured results for these test circuits and discuss design efficiency, potential improvements, and future work.
Abstract Superconducting integrated circuits have long been completely handcrafted or at best designed with a loose collection of tools that require manual manipulation of data and design transfer between tools. Electronic Design Automation (EDA) software development requires significant investment of resources to track the evolution of integrated circuit fabrication processes, which has only been possible commercially for highly successful semiconductor integrated circuit processes. The IARPA SuperTools project which started in 2017 is the largest known investment to date made in superconducting EDA tool development. SuperTools is divided into two main categories: high-level tools for the synthesis of digital logic circuits, clock networks and placed-and-routed layouts for systems such as processors with millions of logic gates; and physical-level tools for the design, simulation, optimisation, verification, layout and parameter extraction of devices and digital logic cells with the inclusion of fabrication process simulation. In this paper the modules developed for the ColdFlux project under SuperTools are discussed from device modelling to chip tape-out. Progress on parameter extraction tools is highlighted.
Josephson Junction (JJ) based superconductor logic families have been proposed and implemented to process analog and digital signals [1] for its low energy dissipation and ultrafast switching speed. Thanks to its construction of resistance-less wires and ultrafast switches, it can operate at clock frequencies of several tens of gigahertz and even hundreds of thousands of times as energy efficient as its CMOS counterparts. It has been perceived to be an important candidate to replace stateof-the-art CMOS due to the superior potential in operation speed and energy efficiency, as recognized by the U.S. IARPA C3 and SuperTools Programs and Japan MEXT-JSPS Project. The design and fabrication of superconducting circuits have already been established [2]-[4]. In addition, a prototype superconducting microprocessor "Core 1" has been demonstrated in 2004 [3], which is able to execute instructions at a high clock frequency of several tens of gigahertz, and with extremely low-power dissipation. These achievements make superconducting electronics highly promising for future high-performance computing applications. As one of the most matured superconducting technology, the Rapid-Single-Flux-Quantum (RSFQ) technology is proposed by K. Likharev, O. Mukhanoc, V. Semenov in 1985 [1]. Despite its capability to be operated at an ultra-high speed of hundreds of GHz while maintaining extremely low switching energy (10^-19 J), it suffers from an increasing static power due to on-chip resistors that are required for constant DC bias supply for the main RSFQ circuit. Numerous methods have been proposed to resolve the static power dissipation problem of RSFQ, including low-voltage RSFQ (LV-RSFQ) [5], reciprocal quantum logic (RQL) [6], LRbiased RSFQ [7] and energy-efficient single-flux quantum (eSFQ) [8]. The Adiabatic Quantum-Flux-Parametron (AQFP) technology, on the other hand, uses AC bias/excitation currents as both multiphase clock signal and power supply [9] to mitigate the power consumption overhead of DC bias while operating at a frequency of few GHz. Consequently, AQFP is remarkably energy efficient compared to RSFQ, albeit operating at a lower frequency. The energy-delay-product (EDP) of the AQFP circuits fabricated using processes such as the AIST standard process 2 (STP2) and the MIT-LL SFQ process [10], [11], is at least 200 times smaller than those of the other energy-efficient superconductor logics and is only three orders of magnitude larger than the quantum limit [9]. Physical testing results of an AQFP 8-bit carry-look-ahead adder and large scale circuits consisting up-to 10,000 AQFP logic gates have demonstrated the AQFP being a promising technology that is robust against circuit parameter variations [12]. Despite the high application potential of AQFP in VLSI circuits, a systematic, automatic synthesis framework for AQFP is imminent. There are two features of AQFP that restrict conventional CMOS synthesis methods being directly applied on AQFP. In spite of And-Or-Inverter(AOI) based representation, which conventional CMOS circuits highly relies on, AQFP circuits prefer majority gates. In fact, its two inputs AND and OR gates are also built with three inputs majority gate with one input being constant. In addition, given its clock-synchronized data propagation nature, AQFP technology requires all inputs to any gate having equal delay. In order to meet this balanced timing requirement, splitters and buffers need to be inserted to the circuit. As a matter of fact, some circuit size can be doubled even with optimum amount of buffers and splitters inserted. The buffer and splitter insertion method can have a huge impact on the overall resource consumption. As the design complexity increases, an unoptimized buffer and splitter insertion method could result in huge amount of unnecessary buffers and splitters added. In addition to a complete synthesis framework, an Integrated Development Environment (IDE) for AQFP design is also lacking. It is imminent to have an IDE for AQFP integrating tools that offer schematic and layout editor, simulation and analysis for better and more efficient AQFP design flow. In this paper, we propose a complete design tool for AQFP design including an Integrated Development Environment (IDE), a complete majority based synthesis framework and a buffer and splitter insertion framework. we propose a majority gates synthesis framework for AQFP circuits that is capable of converting any AOI netlist to its corresponding MAJ netlist by mapping all feasible three-input sub-netlists to corresponding MAJ based implementations. In addition, we also propose an automated buffer and splitter insertion method that is capable of adding the optimum amount of buffers and splitters to any given gate-level netlist. The proposed method can find the minimum amount of buffers and splitters to inserted to achieve equal delay with any library limitation on the size of splitters. Experimental results suggest that the proposed methods can deliver very optimized results. The majority conversion tool can reduce circuit size by an average of 16:47% and delay by 30:21% in average. The buffer and splitter insertion tool only introduces an average of 14:24% overhead in size and 4:70% delay with splitter fanout size limited to 4 compared to an unachievable ideal results with no limitations on splitter fan-out size. Overall, the balanced design in majority gates can be reduced by 23:85% and 29:54% in size and delay compared to its AND/OR/Inverter implemented counterpart.
Single Flux Quantum (SFQ) electronic circuits originated with the advent of Rapid Single Flux Quantum (RSFQ) logic in 1985 and have since evolved to include more energy-efficient technologies such as ERSFQ and eSFQ. SFQ logic circuits, based on the manipulation of quantized flux pulses, have been demonstrated to run at clock speeds in excess of 120 GHz, and with bit-switch energy below 1 aJ. Small SFQ microprocessors have been developed, but characteristics inherent to SFQ circuits and the lack of circuit design tools have hampered the development of large SFQ systems. SFQ circuit characteristics include fan-out of one and the subsequent demand for pulse splitters, gate-level clocking, susceptibility to magnetic fields and sensitivity to intra-gate and inter-gate inductance. Superconducting interconnects propagate data pulses at the speed of light, but suffer from reflections at vias that attenuate transmitted pulses. The recently started IARPA SuperTools program aims to deliver SFQ Computer-Aided Design (CAD) tools that can enable the successful design of 64 bit RISC processors given the characteristics of SFQ circuits. A discussion on the technology of SFQ circuits and the most modern SFQ fabrication processes is presented, with a focus on the unique electronic design automation CAD requirements for the design, layout and verification of SFQ circuits.
Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid single flux quantum) technology and its variants that achieve a verified speed of 370 Ghz, and AC-biased AQFP (adiabatic quantum-flux-parametron) that achieves an energy dissipation near quantum limits. Despite extraordinary characteristics of the superconducting logic families, many technical challenges remain, including the choice of circuit fabrics and architectures that utilize the SFQ technology and the development of effective design automation methodologies and tools. This paper presents our work on developing design flows and tools for DC- and AC-biased SFQ circuits, leveraging unique characteristics and design requirements of the SFQ logic families. More precisely, physical design algorithms, including placement, clock tree routing, and signal routing algorithms targeting RSFQ circuits are presented first. Next, a majority/minority gate-based automatic synthesis framework targeting AQFP logic circuits is described. Finally, experimental results to demonstrate the efficacy of the proposed framework and tools are presented.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.