The recent development of integrated Josephson circuits with increased complexity-e.g. RSFQ devices-invokes the need of a comprehensive computer-aided design support. The derivation of circuit parameters from layout data as well as an efficient and versatile simulation technique are essential means in the design and dimensioning of complex integrated structures. We present a comprehensive solution for calculating circuit parameters and simulating the device dynamics. The calculation of inductances and capacitances is performed by three-dimensional field computation using special developed programs which have been proven in high-T/sub c/ SQUID design. They can process layout information in standard graphic interchange formats (e.g. DXF). The netlists for device simulation can be generated automatically from the equivalent circuit schematic. Additionally, a technique for distributed simulation, which allows performing margins-and-yields-analyses in an efficient manner, was elaborated. The performance of the whole design tool set is demonstrated using basic RSFQ circuits.>
The recent development of integrated Josephson circuits with increased complexity-e.g. RSFQ devices-invokes the need of a comprehensive computer-aided design support. The derivation of circuit parameters from layout data as well as an efficient and versatile simulation technique are essential means in the design and dimensioning of complex integrated structures. We present a comprehensive solution for calculating circuit parameters and simulating the device dynamics. The calculation of inductances and capacitances is performed by three-dimensional field computation using special developed programs which have been proven in high-T/sub c/ SQUID design. They can process layout information in standard graphic interchange formats (e.g. DXF). The netlists for device simulation can be generated automatically from the equivalent circuit schematic. Additionally, a technique for distributed simulation, which allows performing margins-and-yields-analyses in an efficient manner, was elaborated. The performance of the whole design tool set is demonstrated using basic RSFQ circuits.>
New tools have been created to allow a superconducting design flow for schematic design, verification, and optimization. These tools integrate with the Cadence design environment. In single flux quantum superconducting electronics, individual component values, such as wire inductances, Josephson junction critical currents, and bias currents, must be optimized to allow for maximum deviance from the designer value, which is also known as the device margin. One tool is used to create a description of the proper circuit behavior. Included with this tool is the ability to automatically create the description from a Cadence netlist. The other tool is an automated device margin circuit schematic verification and optimization tool, which widens device margins while maintaining proper circuit behavior derived from the first tool. Additionally, this optimization tool can automatically correct the circuit schematic using the proper circuit behavior description. In this paper, the functionality of the language used to create the description of the proper circuit behavior is presented. Several circuits are then verified and optimized based on their correct behavior.
Abstract\nThis diploma work is about Rapid Single Flux Quantum (RSFQ) circuits. This\nsupercoducting digital circuitry has the most promising properties in terms of speed and\npower consumption. The active elements of the RSFQ circuits are Josephson junctions (JJ).\nFor their fabrication low temperature superconducting niobium films are used. Today the\ndesign and fabrication of RSFQ circuits are done in a standardized way with well-defined\ndesign rules. Nevertheless, to design complicated circuits with more than several hundred\njunctions a lot of practical problems must be solved.\nDifferent aspects of the RSFQ circuits design process were investigated in this work.\nIn the theoretical part we propose a new, more realistic model of the Josephson junction for\nphysical simulation (which is necessarily used for design of every RSFQ gate) in order to\nimprove its quality and precision. The new model for the JJ includes additional inductances,\nwhich must reflect a specific environment of the junction layout. The influence of parameter\ndeviations was investigated in the simulation. As sources of the deviation we chose the\nspread of c (the Stewart-McCumber parameter) and that of the inductances. Then the\noperational margins of the basic elements of the RSFQ logic SR flip-flop were determined\nand compared with the prediction of the previously used model. To prove the results of\nsimulations we designed a test structure of the SR flip-flop, with c=1 and c=2 for the wellestablished\nHYPRES technology (USA).\nAnother part of the work is practical measurements. A test chip, containing chains of 100\nJosephson junctions was designed and measured in order to estimate the spread of critical\ncurrents in real technology.
We have investigated various geometrical design dependencies for rapid single-flux-quantum (RSFQ) circuits in high-Tcsuperconductors (HTS) technology, including the characteristics of the intermediate inductances. Structural- and temporal-dependent combinations of Cn-Rn(capacitance and normal resistance of the Josephson junctions, JJs) in the HTS technology are also investigated. Relatively favorable combinations of normal resistance and low capacitance of the JJs needed in the HTS technology for RSFQ circuits have been made possible by recent fabrication methods of high-quality YBCO films. Obtaining these devices is made achievable by using the grain boundary structures and high critical current density (JC) of the HTS JJs. Mutual interactions of the intermediate inductances with other parts of the whole circuit are examined and optimized for the best operation situation. Here in particular, the operation of the HTS Josephson transmission-line (JTL) cells utilizing the grain boundary Josephson junctions, including various structural inductances, is studied based on the reported parameters of the developed devices and thoroughly analyzed by simulation results.
The semiconductor industry standard computer-aided-design (CAD) tool Cadence has been calibrated for a 3 /spl mu/m Niobium technology in order to design and build superconductive single flux quantum (SFQ) circuits. The top-down design methodology includes Verilog functional simulation, schematic capture, graphic layout, functional verification, design rule checking, electrical rule checking, and layout-vs.-schematic verification. This design framework has been used successfully at the University of Rochester in designing more than 15 elementary SFQ cells and three large scale digital and mixed-signal SFQ circuits, demonstrating significant improvement in both design efficiency and accuracy.
Josephson Junction (JJ) based superconductor logic families have been proposed and implemented to process analog and digital signals [1] for its low energy dissipation and ultrafast switching speed. Thanks to its construction of resistance-less wires and ultrafast switches, it can operate at clock frequencies of several tens of gigahertz and even hundreds of thousands of times as energy efficient as its CMOS counterparts. It has been perceived to be an important candidate to replace stateof-the-art CMOS due to the superior potential in operation speed and energy efficiency, as recognized by the U.S. IARPA C3 and SuperTools Programs and Japan MEXT-JSPS Project. The design and fabrication of superconducting circuits have already been established [2]-[4]. In addition, a prototype superconducting microprocessor "Core 1" has been demonstrated in 2004 [3], which is able to execute instructions at a high clock frequency of several tens of gigahertz, and with extremely low-power dissipation. These achievements make superconducting electronics highly promising for future high-performance computing applications. As one of the most matured superconducting technology, the Rapid-Single-Flux-Quantum (RSFQ) technology is proposed by K. Likharev, O. Mukhanoc, V. Semenov in 1985 [1]. Despite its capability to be operated at an ultra-high speed of hundreds of GHz while maintaining extremely low switching energy (10^-19 J), it suffers from an increasing static power due to on-chip resistors that are required for constant DC bias supply for the main RSFQ circuit. Numerous methods have been proposed to resolve the static power dissipation problem of RSFQ, including low-voltage RSFQ (LV-RSFQ) [5], reciprocal quantum logic (RQL) [6], LRbiased RSFQ [7] and energy-efficient single-flux quantum (eSFQ) [8]. The Adiabatic Quantum-Flux-Parametron (AQFP) technology, on the other hand, uses AC bias/excitation currents as both multiphase clock signal and power supply [9] to mitigate the power consumption overhead of DC bias while operating at a frequency of few GHz. Consequently, AQFP is remarkably energy efficient compared to RSFQ, albeit operating at a lower frequency. The energy-delay-product (EDP) of the AQFP circuits fabricated using processes such as the AIST standard process 2 (STP2) and the MIT-LL SFQ process [10], [11], is at least 200 times smaller than those of the other energy-efficient superconductor logics and is only three orders of magnitude larger than the quantum limit [9]. Physical testing results of an AQFP 8-bit carry-look-ahead adder and large scale circuits consisting up-to 10,000 AQFP logic gates have demonstrated the AQFP being a promising technology that is robust against circuit parameter variations [12]. Despite the high application potential of AQFP in VLSI circuits, a systematic, automatic synthesis framework for AQFP is imminent. There are two features of AQFP that restrict conventional CMOS synthesis methods being directly applied on AQFP. In spite of And-Or-Inverter(AOI) based representation, which conventional CMOS circuits highly relies on, AQFP circuits prefer majority gates. In fact, its two inputs AND and OR gates are also built with three inputs majority gate with one input being constant. In addition, given its clock-synchronized data propagation nature, AQFP technology requires all inputs to any gate having equal delay. In order to meet this balanced timing requirement, splitters and buffers need to be inserted to the circuit. As a matter of fact, some circuit size can be doubled even with optimum amount of buffers and splitters inserted. The buffer and splitter insertion method can have a huge impact on the overall resource consumption. As the design complexity increases, an unoptimized buffer and splitter insertion method could result in huge amount of unnecessary buffers and splitters added. In addition to a complete synthesis framework, an Integrated Development Environment (IDE) for AQFP design is also lacking. It is imminent to have an IDE for AQFP integrating tools that offer schematic and layout editor, simulation and analysis for better and more efficient AQFP design flow. In this paper, we propose a complete design tool for AQFP design including an Integrated Development Environment (IDE), a complete majority based synthesis framework and a buffer and splitter insertion framework. we propose a majority gates synthesis framework for AQFP circuits that is capable of converting any AOI netlist to its corresponding MAJ netlist by mapping all feasible three-input sub-netlists to corresponding MAJ based implementations. In addition, we also propose an automated buffer and splitter insertion method that is capable of adding the optimum amount of buffers and splitters to any given gate-level netlist. The proposed method can find the minimum amount of buffers and splitters to inserted to achieve equal delay with any library limitation on the size of splitters. Experimental results suggest that the proposed methods can deliver very optimized results. The majority conversion tool can reduce circuit size by an average of 16:47% and delay by 30:21% in average. The buffer and splitter insertion tool only introduces an average of 14:24% overhead in size and 4:70% delay with splitter fanout size limited to 4 compared to an unachievable ideal results with no limitations on splitter fan-out size. Overall, the balanced design in majority gates can be reduced by 23:85% and 29:54% in size and delay compared to its AND/OR/Inverter implemented counterpart.
InductEx [1] is a software tool used for the analysis of integrated circuit designs and extraction of design parameters by way of numerical electromagnetic field solving. This tool was originally developed with Rapid Single Flux Quantum (RSFQ) chips in mind, but it has a broad applicability and can be extended to other processes. In this poster, we report a comprehensive analysis of a superconducting aluminum two qubit chip. This analysis was performed with InductEx. We report the design of a two qubit chip which has the characteristics necessary to execute single and two qubit gates. Ahead of fabrication, several design characteristics have been extracted from this quantum chip design in order to verify that it satisfies basic design principles of transmon qubits. These characteristics are reported in this poster and they include the calculation of chip anharmonicities, qubit frequencies, resonator frequencies as well as g-factors and dispersive shifts. Design constraints which are satisfied by these extracted parameters are discussed. Additionally, qualitative aspects of the chip have been obtained from current density maps and are reported here. Taken as a whole, this analysis demonstrates the broad applicability of Inductex to integrated circuit design and particularly to the problem of quantum circuit layout optimization.