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IEEE Transactions on Applied Superconductivity

Effects of the Design Parameters on Characteristics of the Inductances and JJs in HTS RSFQ Circuits

Tahereh Jabbari, Faezeh Shanehsazzadeh, Hesam Zandi, M. Banzet, Jürgen Schubert, Mehdi Fardmanesh

Published Jul 30, 2018• 13 citations
Publisher

Abstract

We have investigated various geometrical design dependencies for rapid single-flux-quantum (RSFQ) circuits in high-Tcsuperconductors (HTS) technology, including the characteristics of the intermediate inductances. Structural- and temporal-dependent combinations of Cn-Rn(capacitance and normal resistance of the Josephson junctions, JJs) in the HTS technology are also investigated. Relatively favorable combinations of normal resistance and low capacitance of the JJs needed in the HTS technology for RSFQ circuits have been made possible by recent fabrication methods of high-quality YBCO films. Obtaining these devices is made achievable by using the grain boundary structures and high critical current density (JC) of the HTS JJs. Mutual interactions of the intermediate inductances with other parts of the whole circuit are examined and optimized for the best operation situation. Here in particular, the operation of the HTS Josephson transmission-line (JTL) cells utilizing the grain boundary Josephson junctions, including various structural inductances, is studied based on the reported parameters of the developed devices and thoroughly analyzed by simulation results.

DOI
10.1109/tasc.2018.2856850

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IEEE Transactions on Applied Superconductivity•Jul 15, 2009•2 citations
We have investigated various geometrical design dependencies for rapid single-flux-quantum (RSFQ) circuits in high-Tcsuperconductors (HTS) technology, including the characteristics of the intermediate inductances. Structural- and temporal-dependent combinations of Cn-Rn(capacitance and normal resistance of the Josephson junctions, JJs) in the HTS technology are also investigated. Relatively favorable combinations of normal resistance and low capacitance of the JJs needed in the HTS technology for RSFQ circuits have been made possible by recent fabrication methods of high-quality YBCO films. Obtaining these devices is made achievable by using the grain boundary structures and high critical current density (JC) of the HTS JJs. Mutual interactions of the intermediate inductances with other parts of the whole circuit are examined and optimized for the best operation situation. Here in particular, the operation of the HTS Josephson transmission-line (JTL) cells utilizing the grain boundary Josephson junctions, including various structural inductances, is studied based on the reported parameters of the developed devices and thoroughly analyzed by simulation results.
Abstract\nThis diploma work is about Rapid Single Flux Quantum (RSFQ) circuits. This\nsupercoducting digital circuitry has the most promising properties in terms of speed and\npower consumption. The active elements of the RSFQ circuits are Josephson junctions (JJ).\nFor their fabrication low temperature superconducting niobium films are used. Today the\ndesign and fabrication of RSFQ circuits are done in a standardized way with well-defined\ndesign rules. Nevertheless, to design complicated circuits with more than several hundred\njunctions a lot of practical problems must be solved.\nDifferent aspects of the RSFQ circuits design process were investigated in this work.\nIn the theoretical part we propose a new, more realistic model of the Josephson junction for\nphysical simulation (which is necessarily used for design of every RSFQ gate) in order to\nimprove its quality and precision. The new model for the JJ includes additional inductances,\nwhich must reflect a specific environment of the junction layout. The influence of parameter\ndeviations was investigated in the simulation. As sources of the deviation we chose the\nspread of c (the Stewart-McCumber parameter) and that of the inductances. Then the\noperational margins of the basic elements of the RSFQ logic SR flip-flop were determined\nand compared with the prediction of the previously used model. To prove the results of\nsimulations we designed a test structure of the SR flip-flop, with c=1 and c=2 for the wellestablished\nHYPRES technology (USA).\nAnother part of the work is practical measurements. A test chip, containing chains of 100\nJosephson junctions was designed and measured in order to estimate the spread of critical\ncurrents in real technology.
We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j/sub C/=400 A/cm/sup 2/ and a characteristic voltage of V/sub C/=165 /spl mu/V, the area of the smallest junction is A=24 /spl mu/m/sup 2/. The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j/sub C/ is below /spl plusmn/8%. The margins of the bias current I/sub b/ of the circuits have been experimentally determined and found to be larger than /spl plusmn/24%. At preset, constant values of I/sub b/, the range of a separate bias current I/sub bsw/ fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than /spl plusmn/56%.
We fabricated and tested high-temperature superconducting (HTS) rapid-single-flux-quantum (RSFQ) circuits using interface-engineered Josephson junction (IEJ). The characteristics of high-speed operation were examined by voltage-divider operation based on the toggle-flip-flop circuit. An operation at 155 GHz was obtained at 15 K and the proper functioning of the voltage divider was observed up to 27 K. Temperature dependence of the maximum operation speed was analyzed by circuit simulation with thermal-noise sources. To achieve higher speed operation using a Josephson junction with a higher I/sub c/R/sub n/ product, we also fabricated an RSFQ balanced comparator using IEJ; proper switching characteristics of the circuit was confirmed up to 190 GHz at 30 K. The bias condition dependencies were studied based on the circuit simulations in the relationship of the I/sub c/R/sub n/ product. The results of circuit simulation indicate that a Josephson junction with an I/sub c/R/sub n/ product of more than 0.7 mV is required for high-speed operation (100 GHz) in high-temperature range (30-40 K). We believe that the IEJ is a promising junction candidate for realizing high-speed operation in a high-temperature range.
In the design of electronic applications (for example, rapid single flux quantum (RSFQ) circuits), the properties of Josephson junctions (JJs) provided by technology are the major requirement. The characteristic voltage IcRn an dt he dynamic parameter βc are non-negligibly important, bu tt he external shunted junctions are only completely described by including the parasitic inductance between the junction area and the shunt resistor. The first publications of the RSFQ circuit technique were closely followed by many studies on the dynamic influence of this inductance. It has been pointed out that no practical value of this parameter has to be taken into account in the circuit design and optimization process. The operation of RSFQ logic circuits made of high-temperature superconductors (HTS) are strongly influenced by thermal noise. Our paper contains the determination of the digital bit-error rate for all different types of JJs by using a Fokker–Planck equation for describing the influence of thermal fluctuations. Ou ra nalysis shows that the parasitic inductance cannot be neglected in terms of noise. The intrinsic shunted junctions like high current density-, SINIS- and all kinds of HTS-JJs provide the best noise immunity for a fixed temperature.
We suggest a new design of Rapid Single Flux Quantum (RSFQ) logic circuits which is based on a single superconducting layer and does not require a superconducting ground plane. The small inductances of about 10 pH, that are obligatory for the RSFQ applications, are formed as narrow slits with width comparable to the London penetration depth (/spl cong/0.15 /spl mu/m). The design allows us to decrease the geometric size of the RSFQ cell and can be applied to low-T/sub c/ circuits as well. Test circuits have been implemented using YBaCuO grain boundary junctions on assymmetric 32/spl deg/Y-ZrO/sub 2/ bi-crystals to measure the slit inductance per unit length and the mutual inductance of neighboring slits. A typical inductance of a 0.4 pm slit was determined to be 0.7pH//spl mu/m. We present a new design and a computer simulation of a flip-flop circuit based on these inductance measurements. To realize these circuits experimentally one needs at least two grain boundaries, separated by a distance of 10 to l5 /spl mu/m, or to use bi-epitaxial or step-edge junction technology.>
A high-Tcsuperconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve Icx uniformity. As a result, all circuits were successfully tested and show at least plusmn40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using YBa2Cu3O7-deltaramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.