Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

RSFQ circuitry realized in a SINIS technology process

M. Khabipov, D Balashov, F.-I. Buchholz, W. Kessel, J. Niemeyer

Published Jan 1, 1999• 15 citations
Publisher

Abstract

We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j/sub C/=400 A/cm/sup 2/ and a characteristic voltage of V/sub C/=165 /spl mu/V, the area of the smallest junction is A=24 /spl mu/m/sup 2/. The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j/sub C/ is below /spl plusmn/8%. The margins of the bias current I/sub b/ of the circuits have been experimentally determined and found to be larger than /spl plusmn/24%. At preset, constant values of I/sub b/, the range of a separate bias current I/sub bsw/ fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than /spl plusmn/56%.

DOI
10.1109/77.819338

Related papers

SINIS fabrication process for realizing integrated circuits in RSFQ impulse logic

D Balashov, M. Khabipov, F-Im Buchholz +2 more

At PTB, a new type of fabrication process has been developed to verify rapid single flux quantum (RSFQ) integrated circuits based on intrinsically shunted two-tunnel Josephson junctions (JJs). The process has been realized in LTS implementation using SINIS technology. A variety of single JJs, junction arrays and test circuits have been fabricated and experimentally investigated. The critical current densities of the junctions were set to a nominal value of j C = 500 A cm -2 , with values of the characteristic voltage V C equal to or larger than 160 µV. The JJs show nearly hysteresis-free behaviour (less than 10%); the intrawafer parameter spread is smaller than ±10%. Various basic RSFQ circuits have been realized with operation margins of bias currents of larger than ±20%.

Superconductor Science and Technology•Nov 1, 1999•11 citations

High-frequency performance of RSFQ circuits realized in SINIS technology

M. Khabipov, D Balashov, F.-I. Buchholz +1 more

The paper presents the determination of the high-frequency performance of Rapid Single Flux Quantum (RSFQ) circuits fabricated in superconductor-insulator-normal metal-insulator-superconductor (SINIS) technology. Circuits of different designs have been realized and were experimentally investigated, including specially designed T flip-flop (TFF) structures and circuits consisting of a switch terminated in Josephson transmission lines. For TFF circuits, the operational functionality was investigated in the frequency range from dc up to nearly 200 GHz. Two frequency domains were found. In the first domain, ranging up to frequencies of 80 GHz (f/sub C//spl cong/Y/sub C///spl Phi//sub 0/), correct digital operation of the device was ascertained. Beyond this range a second domain was found, ranging to nearly 200 GHz, for which quasi-analog frequency dividing is assumed. The bias current margins are /spl plusmn/30% at 40 GHz and /spl plusmn/15% between 130 GHz and 200 GHz. For circuits consisting of a switch, the operational functionality was proved in the frequency range from dc up to 50 GHz, with bias current margins of more than /spl plusmn/20%. The critical current density of the circuits is j/sub C//spl cong/750 A/cm/sup 2/. The smallest junction area is about A=12 /spl mu/m/sup 2/, and the characteristic voltage is V/sub C/=170 /spl mu/V.

IEEE Transactions on Applied Superconductivity•Mar 1, 2001•7 citations

SINIS process development for integrated circuits with characteristic voltages exceeding 250 μV

D Balashov, M. Khabipov, F.-I. Buchholz +1 more

At PTB, the fabrication process in Nb-Al/Al/sub x/O/sub y//Al/Al/sub x/O/sub y//Al-Nb SINIS multilayer technology has been improved to raise the characteristic voltage of SINIS two-tunnel Josephson junctions up to V/sub C/=I/sub C/R/sub n/=245 /spl mu/V. The process has been realized in LTS implementation. Various sets of the test wafers and wafers containing dc/SFQ and SFQ/dc converters, Josephson transmission lines, and T-flipflop circuits were fabricated and measured. The critical current densities of the junctions have been varied in the range from 70 A/cm/sup 2/ to 2.2 kA/cm/sup 2/ with corresponding characteristic voltages of V/sub C/=55 /spl mu/V and 245 /spl mu/V at the temperature of 4.2 K. The junctions show nearly hysteresis-free behaviour (less than 15%), the intra-wafer parameter spread is smaller than /spl plusmn/10%. RSFQ circuits have been realized with operation margins of the bias currents larger than /spl plusmn/20%.

IEEE Transactions on Applied Superconductivity•Mar 1, 2001•11 citations

Superconductor digital circuits with π junctions alone

Feng Li, Yuto Takeshita, Masamitsu Tanaka +1 more

We adopt superconductor/ferromagnet/insulator/superconductor (SFIS) Josephson junctions (JJs) as both switching JJs and intrinsic π phase shifters in superconductor digital circuits. The critical current density (Jc) and characteristic voltage (Vc) of the SFIS junctions are about 22 A/cm2 and 22 μV, respectively. The intrinsic π phase shift is confirmed by measuring the suppressed nominal critical current Icn and half-period-shifted modulation pattern of a π–π–π superconducting quantum interference device (SQUID) that contains three π-JJs in a superconducting loop. A single-flux-quantum (SFQ) circuit composed of a DC/SFQ, Josephson transmission line (JTL), and SFQ/DC converter based on SFIS JJs alone is demonstrated at 4.2 K. The energy dissipation of the SFQ/DC converter decreases by 80% because some JJs are self-biased by the π phase shifter. The intrinsic circulating currents induced by the π phase shifters lead to a narrow bias margin (±5%) and even error function, which can be solved by parameters optimization or circuit initialization in the future. The half-modulation period (Φ0/2) of a half-flux-quantum (HFQ) SQUID (a partial HFQ JTL) exhibits propagation of HFQ between π–π–π SQUIDs, indicating that more complex HFQ circuits can be developed with π-JJs alone in the future.

Applied Physics Letters•Apr 17, 2023•10 citations

Experimental realization of a resistive single flux quantum logic circuit

V. P. Koshelets, K. K. Likharev, V. V. Migulin +5 more

An integrated circuit including all basic components of the recently suggested Resistive Single Flux Quantum (RSFQ) logic family has been designed, fabricated and tested successfully. The circuit includes a generator of periodic SFQ pulses, four buffer/amplifier stages for splitting, channeling and regeneration of the pulses, a detector/load stage, and universal RSFQ logic gate (here performing the NOT function). The 10μm design rule circuit employs 13 active Nb - Al2O3- Nb Josephson junctions with the critical current density ∼ 0.5 kA/cm2. externally shunted by Mo resistors with R 1 Ohm. The shunting provided critical damping of the junctions (\beta_{c}\lsim 1) and reasonable (\sim 500 \muV) IcR product. The circuit operation has been tested by measurement of dc voltages\bar{V}_{i}across various Josephson junctions as functions of the dc current through the pulse generator. Correct and stable operation of the circuit for the clock frequencies from 0 to ∼30 GHz has been demonstrated.

IEEE Transactions on Magnetics•Mar 1, 1987•39 citations

9 K operation of RSFQ logic cells fabricated by NbN integrated circuit technology

Hirotaka Terai, Z. Wang

We report on the fabrication and the operation of all-NbN rapid single flux quantum (RSFQ) circuits. The NbN integrated circuit consists of NbN/AlN/NbN tunnel junctions, Mo resistors, sputtered SiO/sub 2/ insulating layers, and 400-nm-thick NbN ground plane and wiring layer. The circuits were fabricated with the minimum junction size of 2 /spl mu/m/spl times/2 /spl mu/m and the alignment margin of +/-0.5 /spl mu/m. We designed RSFQ logic cells under critical current density of 2.5 kA/cm/sup 2/, sheet resistance of 2 /spl Omega/ and sheet inductance of 1.4 pH. We experimentally investigated dc bias margin of the fabricated RSFQ cells at 9 K. We observed relatively large dc bias margin of more than +/-25% for a pulse splitter, a confluence buffer and an RS flip-flop, while the dc bias margin of a T flip-flop was less than +/-5%. We succeeded to demonstrate the operation of 16-bit concurrent flow shift register at 9 K.

IEEE Transactions on Applied Superconductivity•Mar 1, 2001•16 citations
We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j/sub C/=400 A/cm/sup 2/ and a characteristic voltage of V/sub C/=165 /spl mu/V, the area of the smallest junction is A=24 /spl mu/m/sup 2/. The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j/sub C/ is below /spl plusmn/8%. The margins of the bias current I/sub b/ of the circuits have been experimentally determined and found to be larger than /spl plusmn/24%. At preset, constant values of I/sub b/, the range of a separate bias current I/sub bsw/ fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than /spl plusmn/56%.
At PTB, a new type of fabrication process has been developed to verify rapid single flux quantum (RSFQ) integrated circuits based on intrinsically shunted two-tunnel Josephson junctions (JJs). The process has been realized in LTS implementation using SINIS technology. A variety of single JJs, junction arrays and test circuits have been fabricated and experimentally investigated. The critical current densities of the junctions were set to a nominal value of j C = 500 A cm -2 , with values of the characteristic voltage V C equal to or larger than 160 µV. The JJs show nearly hysteresis-free behaviour (less than 10%); the intrawafer parameter spread is smaller than ±10%. Various basic RSFQ circuits have been realized with operation margins of bias currents of larger than ±20%.
The paper presents the determination of the high-frequency performance of Rapid Single Flux Quantum (RSFQ) circuits fabricated in superconductor-insulator-normal metal-insulator-superconductor (SINIS) technology. Circuits of different designs have been realized and were experimentally investigated, including specially designed T flip-flop (TFF) structures and circuits consisting of a switch terminated in Josephson transmission lines. For TFF circuits, the operational functionality was investigated in the frequency range from dc up to nearly 200 GHz. Two frequency domains were found. In the first domain, ranging up to frequencies of 80 GHz (f/sub C//spl cong/Y/sub C///spl Phi//sub 0/), correct digital operation of the device was ascertained. Beyond this range a second domain was found, ranging to nearly 200 GHz, for which quasi-analog frequency dividing is assumed. The bias current margins are /spl plusmn/30% at 40 GHz and /spl plusmn/15% between 130 GHz and 200 GHz. For circuits consisting of a switch, the operational functionality was proved in the frequency range from dc up to 50 GHz, with bias current margins of more than /spl plusmn/20%. The critical current density of the circuits is j/sub C//spl cong/750 A/cm/sup 2/. The smallest junction area is about A=12 /spl mu/m/sup 2/, and the characteristic voltage is V/sub C/=170 /spl mu/V.
At PTB, the fabrication process in Nb-Al/Al/sub x/O/sub y//Al/Al/sub x/O/sub y//Al-Nb SINIS multilayer technology has been improved to raise the characteristic voltage of SINIS two-tunnel Josephson junctions up to V/sub C/=I/sub C/R/sub n/=245 /spl mu/V. The process has been realized in LTS implementation. Various sets of the test wafers and wafers containing dc/SFQ and SFQ/dc converters, Josephson transmission lines, and T-flipflop circuits were fabricated and measured. The critical current densities of the junctions have been varied in the range from 70 A/cm/sup 2/ to 2.2 kA/cm/sup 2/ with corresponding characteristic voltages of V/sub C/=55 /spl mu/V and 245 /spl mu/V at the temperature of 4.2 K. The junctions show nearly hysteresis-free behaviour (less than 15%), the intra-wafer parameter spread is smaller than /spl plusmn/10%. RSFQ circuits have been realized with operation margins of the bias currents larger than /spl plusmn/20%.
We adopt superconductor/ferromagnet/insulator/superconductor (SFIS) Josephson junctions (JJs) as both switching JJs and intrinsic π phase shifters in superconductor digital circuits. The critical current density (Jc) and characteristic voltage (Vc) of the SFIS junctions are about 22 A/cm2 and 22 μV, respectively. The intrinsic π phase shift is confirmed by measuring the suppressed nominal critical current Icn and half-period-shifted modulation pattern of a π–π–π superconducting quantum interference device (SQUID) that contains three π-JJs in a superconducting loop. A single-flux-quantum (SFQ) circuit composed of a DC/SFQ, Josephson transmission line (JTL), and SFQ/DC converter based on SFIS JJs alone is demonstrated at 4.2 K. The energy dissipation of the SFQ/DC converter decreases by 80% because some JJs are self-biased by the π phase shifter. The intrinsic circulating currents induced by the π phase shifters lead to a narrow bias margin (±5%) and even error function, which can be solved by parameters optimization or circuit initialization in the future. The half-modulation period (Φ0/2) of a half-flux-quantum (HFQ) SQUID (a partial HFQ JTL) exhibits propagation of HFQ between π–π–π SQUIDs, indicating that more complex HFQ circuits can be developed with π-JJs alone in the future.
An integrated circuit including all basic components of the recently suggested Resistive Single Flux Quantum (RSFQ) logic family has been designed, fabricated and tested successfully. The circuit includes a generator of periodic SFQ pulses, four buffer/amplifier stages for splitting, channeling and regeneration of the pulses, a detector/load stage, and universal RSFQ logic gate (here performing the NOT function). The 10μm design rule circuit employs 13 active Nb - Al2O3- Nb Josephson junctions with the critical current density ∼ 0.5 kA/cm2. externally shunted by Mo resistors with R 1 Ohm. The shunting provided critical damping of the junctions (\beta_{c}\lsim 1) and reasonable (\sim 500 \muV) IcR product. The circuit operation has been tested by measurement of dc voltages\bar{V}_{i}across various Josephson junctions as functions of the dc current through the pulse generator. Correct and stable operation of the circuit for the clock frequencies from 0 to ∼30 GHz has been demonstrated.
We report on the fabrication and the operation of all-NbN rapid single flux quantum (RSFQ) circuits. The NbN integrated circuit consists of NbN/AlN/NbN tunnel junctions, Mo resistors, sputtered SiO/sub 2/ insulating layers, and 400-nm-thick NbN ground plane and wiring layer. The circuits were fabricated with the minimum junction size of 2 /spl mu/m/spl times/2 /spl mu/m and the alignment margin of +/-0.5 /spl mu/m. We designed RSFQ logic cells under critical current density of 2.5 kA/cm/sup 2/, sheet resistance of 2 /spl Omega/ and sheet inductance of 1.4 pH. We experimentally investigated dc bias margin of the fabricated RSFQ cells at 9 K. We observed relatively large dc bias margin of more than +/-25% for a pulse splitter, a confluence buffer and an RS flip-flop, while the dc bias margin of a T flip-flop was less than +/-5%. We succeeded to demonstrate the operation of 16-bit concurrent flow shift register at 9 K.