At PTB, the fabrication process in Nb-Al/Al/sub x/O/sub y//Al/Al/sub x/O/sub y//Al-Nb SINIS multilayer technology has been improved to raise the characteristic voltage of SINIS two-tunnel Josephson junctions up to V/sub C/=I/sub C/R/sub n/=245 /spl mu/V. The process has been realized in LTS implementation. Various sets of the test wafers and wafers containing dc/SFQ and SFQ/dc converters, Josephson transmission lines, and T-flipflop circuits were fabricated and measured. The critical current densities of the junctions have been varied in the range from 70 A/cm/sup 2/ to 2.2 kA/cm/sup 2/ with corresponding characteristic voltages of V/sub C/=55 /spl mu/V and 245 /spl mu/V at the temperature of 4.2 K. The junctions show nearly hysteresis-free behaviour (less than 15%), the intra-wafer parameter spread is smaller than /spl plusmn/10%. RSFQ circuits have been realized with operation margins of the bias currents larger than /spl plusmn/20%.
At PTB, the fabrication process in Nb-Al/Al/sub x/O/sub y//Al/Al/sub x/O/sub y//Al-Nb SINIS multilayer technology has been improved to raise the characteristic voltage of SINIS two-tunnel Josephson junctions up to V/sub C/=I/sub C/R/sub n/=245 /spl mu/V. The process has been realized in LTS implementation. Various sets of the test wafers and wafers containing dc/SFQ and SFQ/dc converters, Josephson transmission lines, and T-flipflop circuits were fabricated and measured. The critical current densities of the junctions have been varied in the range from 70 A/cm/sup 2/ to 2.2 kA/cm/sup 2/ with corresponding characteristic voltages of V/sub C/=55 /spl mu/V and 245 /spl mu/V at the temperature of 4.2 K. The junctions show nearly hysteresis-free behaviour (less than 15%), the intra-wafer parameter spread is smaller than /spl plusmn/10%. RSFQ circuits have been realized with operation margins of the bias currents larger than /spl plusmn/20%.
At PTB, a new type of fabrication process has been developed to verify rapid single flux quantum (RSFQ) integrated circuits based on intrinsically shunted two-tunnel Josephson junctions (JJs). The process has been realized in LTS implementation using SINIS technology. A variety of single JJs, junction arrays and test circuits have been fabricated and experimentally investigated. The critical current densities of the junctions were set to a nominal value of j C = 500 A cm -2 , with values of the characteristic voltage V C equal to or larger than 160 µV. The JJs show nearly hysteresis-free behaviour (less than 10%); the intrawafer parameter spread is smaller than ±10%. Various basic RSFQ circuits have been realized with operation margins of bias currents of larger than ±20%.
We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j/sub C/=400 A/cm/sup 2/ and a characteristic voltage of V/sub C/=165 /spl mu/V, the area of the smallest junction is A=24 /spl mu/m/sup 2/. The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j/sub C/ is below /spl plusmn/8%. The margins of the bias current I/sub b/ of the circuits have been experimentally determined and found to be larger than /spl plusmn/24%. At preset, constant values of I/sub b/, the range of a separate bias current I/sub bsw/ fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than /spl plusmn/56%.
The SNS (Nb/HfTi/Nb) ramp junction technology process has been improved for digital superconducting circuit operation. DC interferometers were realized on an isolated superconducting ground plane, connections being realized through windows in the insulation layers. The inductances of superconducting Nb striplines (widths w down to the sub-/spl mu/m range) were measured. For a 250 nm SiO/sub 2//Nb-oxide insulation layer, the sheet inductances of striplines were determined at 0.382 /spl plusmn/ 0.009, 0.340 /spl plusmn/ 0.005, and 0.293 /spl plusmn/ 0.008 pH (stripline widths: 1.5, 1.0, 0.54 /spl mu/m) and compared with data calculated by different inductance evaluation programs. The Josephson junctions used in the interferometers exhibit a critical current density of j/sub C/=525 kA/cm/sup 2/ and a characteristic voltage of V/sub C/=95 /spl mu/V. The design of an RSFQ converter circuit was developed on the basis of SNS ramp junction technology. For circuit applications the critical current density j/sub C/ was set to 150 kA/cm/sup 2/.
At PTB, a fabrication process has been developed in SNS Nb/PdAu/Nb technology for the verification of small Josephson junctions (JJs) in the deep sub-micron range to enable the implementation of JJs as active elements in highly integrated superconducting circuits. Two steps of this technological development are described with regard to appropriately designed circuit layouts of JJ series arrays (JJAs), the first one in a conventional window type junction (WTJ) configuration and the second one in a ramp type junction (RTJ) configuration. Test circuits of JJAs containing up to 10 000 JJs have been fabricated and experimentally tested. In WTJ configuration, the circuits proved to be sensitive to external perturbing effects affecting the stability of circuit operation. In contrast to that, in RTJ configuration, the circuits realized showed correct function and a high grade of reliability of operation. To produce RTJ circuits, the technology parameters have been set to realize JJs with contact areas of A = 0.25 µm × 1.3 µm. At a thickness of the PdAu normal metal layer of d = 40 nm, the values achieved for the critical current density and for the product of critical current and normal state resistance are about jc = 200 kA cm-2 and about Ic RN = 21 µV.
The paper presents the determination of the high-frequency performance of Rapid Single Flux Quantum (RSFQ) circuits fabricated in superconductor-insulator-normal metal-insulator-superconductor (SINIS) technology. Circuits of different designs have been realized and were experimentally investigated, including specially designed T flip-flop (TFF) structures and circuits consisting of a switch terminated in Josephson transmission lines. For TFF circuits, the operational functionality was investigated in the frequency range from dc up to nearly 200 GHz. Two frequency domains were found. In the first domain, ranging up to frequencies of 80 GHz (f/sub C//spl cong/Y/sub C///spl Phi//sub 0/), correct digital operation of the device was ascertained. Beyond this range a second domain was found, ranging to nearly 200 GHz, for which quasi-analog frequency dividing is assumed. The bias current margins are /spl plusmn/30% at 40 GHz and /spl plusmn/15% between 130 GHz and 200 GHz. For circuits consisting of a switch, the operational functionality was proved in the frequency range from dc up to 50 GHz, with bias current margins of more than /spl plusmn/20%. The critical current density of the circuits is j/sub C//spl cong/750 A/cm/sup 2/. The smallest junction area is about A=12 /spl mu/m/sup 2/, and the characteristic voltage is V/sub C/=170 /spl mu/V.
Abstract Achieving high effective characteristic voltage V eff , self-shunted operation, and good wafer-level uniformity simultaneously remains a challenge for Nb-based Josephson junctions for high-speed, large-scale superconducting integrated circuit applications. In this work, V eff = I c R eff characterizes the junction dynamics near the operating point, where R eff is the local differential resistance evaluated at I c . To address this issue, self-shunted Nb/Al–AlN/Al–AlN/Nb junctions were fabricated on 4-inch wafers using reactive magnetron sputtering and a planarized fabrication process. The influences of symmetric AlN barrier thickness, barrier asymmetry, and Al interlayer thickness on the junction characteristics were systematically investigated. J c was found to depend approximately exponentially on the symmetric AlN barrier thickness, whereas V eff exhibited an approximately linear dependence. For asymmetric junctions, J c remained mainly governed by the total barrier thickness, while barrier asymmetry enhanced V eff . In addition, pronounced non-monotonic variations in both J c and V eff were observed as the Al interlayer deposition time was varied, revealing an additional process degree of freedom for performance optimization. Based on the wafer-scale distributions of electrical parameters, a SINIS junction exhibiting a favorable balance between effective characteristic voltage and uniformity was identified, with J c = 2.55 kA cm −2 , V eff = 0.65 mV, and relative standard deviations of 8.1% for J c and 6.7% for V eff . These results provide a practical basis for the development of higher-performance and more highly integrated superconducting circuits.