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Superconductor Science and Technology

Multi-parameter optimization of Nb-based SINIS junctions for high effective characteristic voltage and wafer-level uniformity

Junrong Zhao, Mingfan Chen, Xue Zhang, Maoxiang Chen, Linxian Ma, Hui Xie, Weifeng Shi, Feng Zhou, Liliang Ying, Jie Ren

Published Aug 20, 2026• 0 citations
Publisher

Abstract

Abstract Achieving high effective characteristic voltage V eff , self-shunted operation, and good wafer-level uniformity simultaneously remains a challenge for Nb-based Josephson junctions for high-speed, large-scale superconducting integrated circuit applications. In this work, V eff = I c R eff characterizes the junction dynamics near the operating point, where R eff is the local differential resistance evaluated at I c . To address this issue, self-shunted Nb/Al–AlN/Al–AlN/Nb junctions were fabricated on 4-inch wafers using reactive magnetron sputtering and a planarized fabrication process. The influences of symmetric AlN barrier thickness, barrier asymmetry, and Al interlayer thickness on the junction characteristics were systematically investigated. J c was found to depend approximately exponentially on the symmetric AlN barrier thickness, whereas V eff exhibited an approximately linear dependence. For asymmetric junctions, J c remained mainly governed by the total barrier thickness, while barrier asymmetry enhanced V eff . In addition, pronounced non-monotonic variations in both J c and V eff were observed as the Al interlayer deposition time was varied, revealing an additional process degree of freedom for performance optimization. Based on the wafer-scale distributions of electrical parameters, a SINIS junction exhibiting a favorable balance between effective characteristic voltage and uniformity was identified, with J c = 2.55 kA cm −2 , V eff = 0.65 mV, and relative standard deviations of 8.1% for J c and 6.7% for V eff . These results provide a practical basis for the development of higher-performance and more highly integrated superconducting circuits.

DOI
10.1088/1361-6668/ae9c74

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Abstract Achieving high effective characteristic voltage V eff , self-shunted operation, and good wafer-level uniformity simultaneously remains a challenge for Nb-based Josephson junctions for high-speed, large-scale superconducting integrated circuit applications. In this work, V eff = I c R eff characterizes the junction dynamics near the operating point, where R eff is the local differential resistance evaluated at I c . To address this issue, self-shunted Nb/Al–AlN/Al–AlN/Nb junctions were fabricated on 4-inch wafers using reactive magnetron sputtering and a planarized fabrication process. The influences of symmetric AlN barrier thickness, barrier asymmetry, and Al interlayer thickness on the junction characteristics were systematically investigated. J c was found to depend approximately exponentially on the symmetric AlN barrier thickness, whereas V eff exhibited an approximately linear dependence. For asymmetric junctions, J c remained mainly governed by the total barrier thickness, while barrier asymmetry enhanced V eff . In addition, pronounced non-monotonic variations in both J c and V eff were observed as the Al interlayer deposition time was varied, revealing an additional process degree of freedom for performance optimization. Based on the wafer-scale distributions of electrical parameters, a SINIS junction exhibiting a favorable balance between effective characteristic voltage and uniformity was identified, with J c = 2.55 kA cm −2 , V eff = 0.65 mV, and relative standard deviations of 8.1% for J c and 6.7% for V eff . These results provide a practical basis for the development of higher-performance and more highly integrated superconducting circuits.
To increase the integration scale of superconductor electronics, we are developing a new node, titled SFQ7ee, of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the possible inductor number density above a hundred million inductors per cm2. Increasing the Josephson junction number density to the same level requires implementing self-shunted high-JcJosephson junctions. We investigated the properties of Nb/NbNx/Nb trilayer junctions as a potential replacement of high-JcNb/Al-AlOx/Nb junctions, where NbNxis a disordered, overstoichiometric, nonsuperconducting nitride deposited by reactive sputtering. Dependences of theIcRnproduct and Josephson critical current density, Jc on the NbNx barrier thickness and temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated junctions can be well described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbNxinterfaces and a Cooper pair decay length in the NbNx barrier, ξnTcof about 2.3 nm. Current-voltage characteristics of the junctions are well described by the resistively and capacitively shunted junction (RCSJ) model without excess current. In the studied rangeJc2, the Nb/NbNx/Nb junctions have lower values of the specific resistanceRnA, lower IcRn products, and a stronger dependence of theIcRnon temperature than the self-shunted or critically damped externally shunted Nb/Al-AlOx/Nb junctions with the same critical current density; A is the junction area,Icthe junction critical current, and Rnthe effective shunting resistance.
Improved Characteristics of Intrinsically Shunted Nb/Al−AlOx−Nb{\rm Nb/Al}-{\rm AlO}_{x}-{\rm Nb}Nb/Al−AlOx​−Nb Josephson Junctions
Josephson junctions with non-hysteretic current-voltage characteristics form the basis of most superconducting electronic circuits including RSFQ logic and programmable Josephson voltage standards. In contrast to conventional SIS devices, Nb/Al-AlOx-Nb (SNIS) junctions with an additional comparatively thick Al interlayer and a comparatively thin barrier AlOxare intrinsically shunted at T ≥ 4.2 K . In this contribution, we provide experimental and theoretical arguments proving that this finding is mainly explained by a broad distribution of highly-conductive barrier transparencies with a significant effect from nearly ballistic modes. An additional advantage of the proposed SNIS junctions is possibility to tune the critical voltage value by modifying Nb and/or Al film thicknesses. With observations of wide Shapiro steps up to 1.25 V at 6.3 K we show that this type of Josephson junctions can be successfully used at temperatures above 4.2 K. The presence of well-developed quantized voltage features even at 7.2 K means that Nb/Al-AlOx-Nb devices can successfully operate far above the liquid helium temperature and, in principle, are compatible with two-stage cryocoolers.
Abstract We report on the electrical properties of NbN/TaN/NbN Josephson junctions grown on thermally oxidized silicon substrates, along with the design and fabrication of superconducting single-flux-quantum (SFQ) circuits based on these NbN superconductor/normal metal/superconductor (SNS) junctions. The critical current density ( J c ) of the junctions was found to be relatively sensitive to the barrier thickness, decreasing from 108.0 ± 8.1 kA cm −2 for a 15 nm barrier to 12.8 ± 1.9 kA cm −2 for a 30 nm barrier. For a J c of approximately 24.5 ± 2.1 kA cm −2 and a barrier thickness of 25 nm, the NbN SNS junctions are self-shunted and exhibit nonhysteretic current–voltage ( I – V ) characteristics. Especially for junctions with diameter ( φ ) ranging from 0.8 to 1.6 μ m, their critical current ( I c ) falls within the range of 110–450 μ A, making them suitable for SFQ circuits. By considering the impact of excess current and incorporating it as an additional term in the conventional resistively and capacitively shunted junction model, the I – V curves of NbN SNS junctions can be precisely described, successfully minimizing the deviation between simulations and test results. The DC-SFQ and SFQ-DC interface circuits can both operate normally, and the bias margins of cell circuits such as Josephson transmission line, confluence buffer, D flip-flop, and splitter are greater than 40%. Compared to Nb superconductor/insulator/superconductor junctions, their self-shunting characteristics and relatively thick 25 nm barriers can also enhance the integration of circuits and increase the yield to complex circuits.
We present characteristics of overdamped Josephson junctions consisting of Nb/AlOx/Al/ AlOx/Nb structures. The junctions were fabricated using a well-developed Nb/AlOx/Nb-junction technology and showed well-defined Josephson characteristics at 4.2 K. The characteristic voltage Vc [the product of the critical current Ic and the effective normal resistance Rn(eff)] of junctions, which determines high-frequency performance of the junction, was in the range of 0.1–0.5 mV, and the critical current density Jc in the range of 102–104 A/cm2. Maximum-to-minimum variations in Ic over a wafer were ±4% for junctions with Vc=0.15 mV and ±13% for junctions with Vc=0.5 mV.
NbN-TaN-Nb(Ti)N non-hysteretic SNS Josephson junctions with TaXN barriers tuned through nitrogen content at metal-insulator transition have been produced in a reliable way with characteristic voltage RNICabove 1.5 mV at 9 K. Barriers are typically 7-10 nm thick and Jc in the range 5 to 25 kA/cm-2making feasible LSI RSFQ ADC circuit integration by using the lithographic tools of the Leti C-MOS platform. Junction tri-layers, NbTiN ground-plane and wiring levels have been reactively sputtered and optimized at 300°C in a reproducible way on 8-inch oxidized silicon wafers. A deep UV stepper combined with SF6 gas mixtures RIE has been used to achieve low spread lithography in junction diameters of 716 nm (3σ ~ 40 nm), of 465 nm (3σ ~ 84 nm) across the 8-inch. A well controlled CMP planarization process has been developed on thick PE-CVD silica layers deposited on each superconducting nitride layer. On-line FIB-SEM observations and electrical characterizations associated to the development of a technology test vehicle demonstrate the feasibility of the complete process. The reliable production of nitrides LSI RSFQ circuits such as ADCs and integrated imagers operating in a relaxed cryogenic environment in the 6-10 K temperature range is foreseen to open new telecoms and medical applications. Moreover, a new MgO-AlN-MgO layered insulating barrier junction is shown to operate above 10 K and will be developed for analog front-end circuit parts.
Abstract Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current I c variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ≡ σ I c / I c ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown σ I c / I c = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having σ I c / I c < 1.0% (equivalent to σ f / f < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.