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Superconductor Science and Technology

Superconductor-normal metal-superconductor process development for the fabrication of small Josephson junctions in ramp type configuration

R. Pöpel, Daniel Hagedorn, Thomas Weimann, F.-M. Buchholz, J. Niemeyer

Published Jan 19, 2000• 20 citations
Publisher

Abstract

At PTB, a fabrication process has been developed in SNS Nb/PdAu/Nb technology for the verification of small Josephson junctions (JJs) in the deep sub-micron range to enable the implementation of JJs as active elements in highly integrated superconducting circuits. Two steps of this technological development are described with regard to appropriately designed circuit layouts of JJ series arrays (JJAs), the first one in a conventional window type junction (WTJ) configuration and the second one in a ramp type junction (RTJ) configuration. Test circuits of JJAs containing up to 10 000 JJs have been fabricated and experimentally tested. In WTJ configuration, the circuits proved to be sensitive to external perturbing effects affecting the stability of circuit operation. In contrast to that, in RTJ configuration, the circuits realized showed correct function and a high grade of reliability of operation. To produce RTJ circuits, the technology parameters have been set to realize JJs with contact areas of A = 0.25 µm × 1.3 µm. At a thickness of the PdAu normal metal layer of d = 40 nm, the values achieved for the critical current density and for the product of critical current and normal state resistance are about jc = 200 kA cm-2 and about Ic RN = 21 µV.

DOI
10.1088/0953-2048/13/2/305

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At PTB, a fabrication process has been developed in SNS Nb/PdAu/Nb technology for the verification of small Josephson junctions (JJs) in the deep sub-micron range to enable the implementation of JJs as active elements in highly integrated superconducting circuits. Two steps of this technological development are described with regard to appropriately designed circuit layouts of JJ series arrays (JJAs), the first one in a conventional window type junction (WTJ) configuration and the second one in a ramp type junction (RTJ) configuration. Test circuits of JJAs containing up to 10 000 JJs have been fabricated and experimentally tested. In WTJ configuration, the circuits proved to be sensitive to external perturbing effects affecting the stability of circuit operation. In contrast to that, in RTJ configuration, the circuits realized showed correct function and a high grade of reliability of operation. To produce RTJ circuits, the technology parameters have been set to realize JJs with contact areas of A = 0.25 µm × 1.3 µm. At a thickness of the PdAu normal metal layer of d = 40 nm, the values achieved for the critical current density and for the product of critical current and normal state resistance are about jc = 200 kA cm-2 and about Ic RN = 21 µV.
Several applications of Josephson junctions (JJs) in low-temperature superconducting circuits such as programmable voltage standards and SFQ logical circuits or SQUID sensors require JJs with sub-µm dimensions. A method for preparing superconductor-isolator-superconductor (SIS) JJs as well as superconductor-normal metal-superconductor (SNS) JJs was developed which allows the preparation of both types of junctions by nearly the same technological process. Titanium is used as the normal metal for the SNS JJ. Ti can be anodically oxidized and a technology similar to the well-tried Nb-Al technology for SIS JJs can be applied to the SNS system, too. By electron-beam exposure of a negative deep UV photoresist (ma-N 2400) a stable resist mask is generated which has to withstand the following three self-aligned process steps: etching of the Nb counterelectrode by RIE, isolation by anodization and lifting of a SiO planarization layer. By this process SNS (Nb-Ti-Nb) and SIS (Nb-Al/AlO x -Nb) Josephson junctions with smallest junction areas of 0.49 µm 2 were prepared and characterized by dc measurements and under the influence of microwave irradiation. The Nb-Ti-Nb junctions have I c R n products of 87 µV. They can be used for programmable Josephson voltage standard circuits at frequencies of 70 GHz.
The SNS (Nb/HfTi/Nb) ramp junction technology process has been improved for digital superconducting circuit operation. DC interferometers were realized on an isolated superconducting ground plane, connections being realized through windows in the insulation layers. The inductances of superconducting Nb striplines (widths w down to the sub-/spl mu/m range) were measured. For a 250 nm SiO/sub 2//Nb-oxide insulation layer, the sheet inductances of striplines were determined at 0.382 /spl plusmn/ 0.009, 0.340 /spl plusmn/ 0.005, and 0.293 /spl plusmn/ 0.008 pH (stripline widths: 1.5, 1.0, 0.54 /spl mu/m) and compared with data calculated by different inductance evaluation programs. The Josephson junctions used in the interferometers exhibit a critical current density of j/sub C/=525 kA/cm/sup 2/ and a characteristic voltage of V/sub C/=95 /spl mu/V. The design of an RSFQ converter circuit was developed on the basis of SNS ramp junction technology. For circuit applications the critical current density j/sub C/ was set to 150 kA/cm/sup 2/.
Superconductor-normal metal-superconductor (SNS) junctions are well-suited for large-scale integrated superconducting circuits. Potential applications are programmable voltage standards, digital-to-analog converters and large-scale RSFQ circuits. The application of SNS junctions provides some advantages, e.g. a simplified fabrication technology and reduced parasitic inductances. But it requires a technological process with dimensions down to the submicrometer region to achieve sufficiently high characteristic voltages I/sub C/R/sub N/. In our process the normal metal interlayer is titanium. Therefore the sidewall insulation of the junctions can be made by anodization, as it is known from the Nb-Al technology. Nb-Ti-Nb Josephson junctions and junction arrays were fabricated down to the submicrometer range with I/sub C/R/sub N/ values up to 87 microvolt depending on the titanium thickness. Their measured critical currents have a small spread of about 10 percent. Shapiro steps are observed under the influence of microwave irradiation. For the application of such junctions in a programmable Josephson voltage standard a new type of microwave circuit using coplanar strips is proposed and successfully tested in 10 V SIS circuits.
At PTB, a new type of fabrication process has been developed to verify rapid single flux quantum (RSFQ) integrated circuits based on intrinsically shunted two-tunnel Josephson junctions (JJs). The process has been realized in LTS implementation using SINIS technology. A variety of single JJs, junction arrays and test circuits have been fabricated and experimentally investigated. The critical current densities of the junctions were set to a nominal value of j C = 500 A cm -2 , with values of the characteristic voltage V C equal to or larger than 160 µV. The JJs show nearly hysteresis-free behaviour (less than 10%); the intrawafer parameter spread is smaller than ±10%. Various basic RSFQ circuits have been realized with operation margins of bias currents of larger than ±20%.
At PTB, the fabrication process in Nb-Al/Al/sub x/O/sub y//Al/Al/sub x/O/sub y//Al-Nb SINIS multilayer technology has been improved to raise the characteristic voltage of SINIS two-tunnel Josephson junctions up to V/sub C/=I/sub C/R/sub n/=245 /spl mu/V. The process has been realized in LTS implementation. Various sets of the test wafers and wafers containing dc/SFQ and SFQ/dc converters, Josephson transmission lines, and T-flipflop circuits were fabricated and measured. The critical current densities of the junctions have been varied in the range from 70 A/cm/sup 2/ to 2.2 kA/cm/sup 2/ with corresponding characteristic voltages of V/sub C/=55 /spl mu/V and 245 /spl mu/V at the temperature of 4.2 K. The junctions show nearly hysteresis-free behaviour (less than 15%), the intra-wafer parameter spread is smaller than /spl plusmn/10%. RSFQ circuits have been realized with operation margins of the bias currents larger than /spl plusmn/20%.
Development of 15kA/cm2^22 Fabrication Process for Superconducting Integrated Digital Circuits
A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3 ΩΩΩ, followed by the deposition of Nb/Al-AlOx_xx​/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm2^22. To increase the Al-AlOx_xx​ barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.