Abstract To meet the specification of the qubits in our laboratory, a 0.4 kA·cm −2 superconducting rapid single flux quantum (RSFQ) circuit was designed and successfully fabricated with an improved Nb‐based self‐aligned lift‐off process. This circuit consists of a single‐flux‐quantum (SFQ) pulse generator, a Josephson transmission line (JTL) and a T‐flip flop (TFF), and it acts as a frequency divider. The values of the inductors in this circuit were extracted using InductEX and the basic function of this circuit was confirmed using the simulation software WRspice before fabrication. After fabrication, the basic parameters of this circuit were measured at ~ 2.5 K in a Janis He‐3 cryostat. This work laid the theoretical and experimental basis for the future research on the RSFQ‐qubit control circuits.
Abstract To meet the specification of the qubits in our laboratory, a 0.4 kA·cm −2 superconducting rapid single flux quantum (RSFQ) circuit was designed and successfully fabricated with an improved Nb‐based self‐aligned lift‐off process. This circuit consists of a single‐flux‐quantum (SFQ) pulse generator, a Josephson transmission line (JTL) and a T‐flip flop (TFF), and it acts as a frequency divider. The values of the inductors in this circuit were extracted using InductEX and the basic function of this circuit was confirmed using the simulation software WRspice before fabrication. After fabrication, the basic parameters of this circuit were measured at ~ 2.5 K in a Janis He‐3 cryostat. This work laid the theoretical and experimental basis for the future research on the RSFQ‐qubit control circuits.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
Abstract\nThis diploma work is about Rapid Single Flux Quantum (RSFQ) circuits. This\nsupercoducting digital circuitry has the most promising properties in terms of speed and\npower consumption. The active elements of the RSFQ circuits are Josephson junctions (JJ).\nFor their fabrication low temperature superconducting niobium films are used. Today the\ndesign and fabrication of RSFQ circuits are done in a standardized way with well-defined\ndesign rules. Nevertheless, to design complicated circuits with more than several hundred\njunctions a lot of practical problems must be solved.\nDifferent aspects of the RSFQ circuits design process were investigated in this work.\nIn the theoretical part we propose a new, more realistic model of the Josephson junction for\nphysical simulation (which is necessarily used for design of every RSFQ gate) in order to\nimprove its quality and precision. The new model for the JJ includes additional inductances,\nwhich must reflect a specific environment of the junction layout. The influence of parameter\ndeviations was investigated in the simulation. As sources of the deviation we chose the\nspread of c (the Stewart-McCumber parameter) and that of the inductances. Then the\noperational margins of the basic elements of the RSFQ logic SR flip-flop were determined\nand compared with the prediction of the previously used model. To prove the results of\nsimulations we designed a test structure of the SR flip-flop, with c=1 and c=2 for the wellestablished\nHYPRES technology (USA).\nAnother part of the work is practical measurements. A test chip, containing chains of 100\nJosephson junctions was designed and measured in order to estimate the spread of critical\ncurrents in real technology.
A simple test circuit of the rapid single-flux-quantum (RSFQ) logic family has been implemented in a planarized all-refractory technology using only two superconducting layers and small Nb/AlOx/Nb Josephson junctions (nominally 1.5×1.5 μm2) with critical current density jc≊6 kA/cm2. A special layout design of the integrated circuit (including a SFQ pulse generator, Josephson transmission line, and T flip–flop) was used to reduce 3D inductances resulting from absence of the ground plane. For samples with various junction parameters, the maximum frequency of the SFQ pulse train, which could be divided by 2 by the flip–flop, ranged from 200 to 370 GHz.
Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>
Several novel circuits of the rapid single-flux-quantum (RSFQ) family of Josephson-junction digital devices have been designed, fabricated using a 2.5- mu m 1000-A/cm/sup 2/ Nb trilayer technology, and tested at low frequencies. Numerical simulation and measurements have shown that these circuits have considerably wider parameter margins, due to application of several novel design methods. The authors have also carried out an experiment to measure the rate of errors in a simple RSFQ circuit including an inverter, confluence buffer, and Josephson transmission line. Near the middle of the parameter window at 4.2 K, the error probability was definitely lower than 3*10/sup -15/ per logic operation, despite experimentation with rudimentary shielding and filtering.>
An integrated circuit including all basic components of the recently suggested Resistive Single Flux Quantum (RSFQ) logic family has been designed, fabricated and tested successfully. The circuit includes a generator of periodic SFQ pulses, four buffer/amplifier stages for splitting, channeling and regeneration of the pulses, a detector/load stage, and universal RSFQ logic gate (here performing the NOT function). The 10μm design rule circuit employs 13 active Nb - Al2O3- Nb Josephson junctions with the critical current density ∼ 0.5 kA/cm2. externally shunted by Mo resistors with R 1 Ohm. The shunting provided critical damping of the junctions (\beta_{c}\lsim 1) and reasonable (\sim 500 \muV) IcR product. The circuit operation has been tested by measurement of dc voltages\bar{V}_{i}across various Josephson junctions as functions of the dc current through the pulse generator. Correct and stable operation of the circuit for the clock frequencies from 0 to ∼30 GHz has been demonstrated.