Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Physica C Superconductivity

Engineering issues in high-frequency RSFQ circuits

T. Van Duzer, L Zheng, Xiangchao Meng, C Loyo, Stephen R. Whiteley, Yu Lei, N. Newman, J. M. Rowell, Nobuyuki Yoshikawa

Published Aug 1, 2002• 16 citations
Publisher
DOI
10.1016/s0921-4534(02)00686-x

Related papers

RSFQ interface circuit for the high-frequency signal output

Yoshinobu Tarutani, Kazuo Saitoh, Kazumasa Takagi

Physica C Superconductivity•Aug 1, 2001•1 citation

Asynchronous Dynamic Single-Flux Quantum Majority Gates

Gleb Krylov, Eby G. Friedman

Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.

IEEE Transactions on Applied Superconductivity•Mar 4, 2020•39 citations

Noise consideration in RSFQ circuits

V. K. Kaplunenko

Physica C Superconductivity•Aug 1, 2002•1 citation

High-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm2 Nb Process Technology

Masamitsu Tanaka, Kitayama Atsushi, Masakazu Okada +4 more

We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.

IEICE Transactions on Electronics•Jan 1, 2014•8 citations

Design of SFQ Circuits and Their Measurement

Kazunori Miyahara, Shuichi Nagasawa, H. Hasegawa +3 more

IEICE Transactions on Electronics•Mar 1, 2002•0 citations

Design issues for interconnects in densely packaged RSFQ structures

Boyko Dimov, Thomas Ortlepp, Hannes Toepfer +1 more

The manufacturing process of LTS RSFQ circuits is quite similar to that of the semiconductor chips, thus providing the possibility of an ultra high-density packaging similar to the modern semiconductor logic circuits. However, the miniaturization of the interconnects does not enhance their performance. The present work highlights the impact of the parasitic interactions between the superconductive interconnects on the correct logical functionality and the upper bias current margins of the LTS RSFQ circuits.

IEEE Transactions on Applied Superconductivity•Jun 1, 2003•7 citations
Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.
We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.
The manufacturing process of LTS RSFQ circuits is quite similar to that of the semiconductor chips, thus providing the possibility of an ultra high-density packaging similar to the modern semiconductor logic circuits. However, the miniaturization of the interconnects does not enhance their performance. The present work highlights the impact of the parasitic interactions between the superconductive interconnects on the correct logical functionality and the upper bias current margins of the LTS RSFQ circuits.