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IEICE Transactions on Electronics

High-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm2 Nb Process Technology

Masamitsu Tanaka, Kitayama Atsushi, Masakazu Okada, Kouketsu Tomohito, Takumi Takinami, Masato ITO, Akira Fujimaki

Published Jan 1, 2014• 8 citations
Publisher

Abstract

We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.

DOI
10.1587/transele.e97.c.166

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We report the successful operation of a low-power arithmetic logic unit (ALU) based on a low-voltage rapid single-flux-quantum (LV-RSFQ) logic circuit, whereby a dc bias current is fed to circuits from lowered constant-voltage sources through small resistors. Both the static and dynamic energy consumptions are reduced because of the reduction in the amplitudes of voltage pulses across the Josephson junctions, with a trade-off of slightly slower switching speeds. The designed bias voltage was set to 0.25mV, which is one-tenth that of our standard RSFQ circuit design. We investigated several issues related to such low-voltage operation, including margins and timing design. To achieve successful operation, we tuned the circuit parameters in the logic gate design and carefully controlled the timing by considering the interference of pulse signals. We show test results for the low-voltage ALU in on-chip high-speed testing. The circuit was fabricated using the AIST Nb/AlOx/Nb Advanced Process with a critical current density of 10kA/cm2. We verified that arithmetic and logical operations were correctly implemented and obtained dc bias margins of 18% at a target clock frequency of 20GHz and achieved a maximum clock frequency of 28GHz with a power consumption of 28µW. These experimental results indicate energy efficiency of 3.6 times that of the standard RSFQ circuit design.
We report successful operations of low-energy consumption rapid single-flux-quantum (RSFQ) circuits applying lowered driving voltages, called LV-RSFQ, using different fabrication processes. In the LV-RSFQ, we feed bias currents to Josephson junctions from lowered constant voltages (less than 1 mV) through small resistors without extra inductors. Both static and dynamic energy consumption are reduced because of suppression of amplitudes of SFQ pulses, in exchange for slower switching speed. We show that the switching speed in LV-RSFQ circuits is improved by increasing critical current density of Josephson junctions. We demonstrated high-speed operations of LV-RSFQ shift registers in a range of 5-40 GHz and 15-90 GHz using the 2.5-kA/cm2and 10-kA/cm2fabrication technologies, respectively. Comparison of the experimental results of the LV-RSFQ circuits fabricated using two different technologies derives the optimum bias voltage in terms of energy-delay product ranged from 0.1 to 1.0ICRS, whereICRSis the product of Josephson critical current and shunt resistance.
Rapid Single-Flux-Quantum Circuits Fabricated Using 20-kA/cm2\hbox{20}\hbox{-}\hbox{kA}/\hbox{cm}^{2}20-kA/cm2 Nb/AlOx/Nb\hbox{Nb}/\hbox{AlO}_{x}/\hbox{Nb}Nb/AlOx​/Nb Process
We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm2process based on conventional Nb/AlOx/Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.
A high-throughput 4$\boldsymbol{\times }4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm\boldsymbol{^2},Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134, Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134,Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134\boldsymbol{\mu }W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40W, respectively. Although the switching speed of the Josephson junctions was reduced by 40W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40\boldsymbol{\%}$owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.
We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU) based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV-RSFQ) approaches. We implemented the ALU using a 10-kA/cm2Nb process. The bias voltage was optimized to obtain high energy efficiency. Although lowed bias voltage leads to difficulty in timing design, we solved the problem by precise timing control. The operating frequency reached 30 GHz. Thanks to these high-throughput and low-energy technologies, we realized highly energy-efficient operation over 100 tera-operations per second per watt (TOPS/W).
We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1 bit arithmetic logic unit (ALU) block. The circuit consists of three DC current driven SFQ switches and a half-adder. We successfully tested the half-adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half-adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached two switches at the input ports of the half-adder to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this set-up, the circuit was successfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES 1 kA cm −2 Nb Josephson junction fabrication process.
A 4-bit bit-slice arithmetic logic unit (ALU) for 32-bit rapid single-flux-quantum microprocessors was demonstrated. The proposed ALU covers all of the ALU operations for the MIPS32 instruction set. It processes bit-sliced 32-bit data that are divided into eight slices of 4 bits. The bit-slice approach simplifies the circuit structure and reduces the hardware cost. The ALU uses synchronous concurrent-flow clocking and consists of eight pipeline stages. It was implemented using the 1.0-μm Nb/AlOx/Nb nine-layer advanced process 2 (ADP2) with a critical current density of 10 kA/cm2, and fabricated by National Institute of Advanced Industrial Science and Technology (AIST). It consists of 3481 Josephson junctions with an area of 3.09 × 1.66 mm2. It achieved the target frequency of 50 GHz and a latency of 524 ps for a 32-bit operation, at the designed DC bias voltage of 2.5 mV, via precise control of interconnect delays and clock distribution. Furthermore, it achieved a throughput of 6.25 × 10932-bit operations per second. All the correct ALU operations with measured DC bias voltage margins of around 10% at 50 GHz were successfully obtained. The proposed ALU can be used for any 4n-bit processing.