Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.
Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
We have developed a cell library for superconducting large scale integrated (LSI) digital circuits based on Single Flux Quantum (SFQ) devices. The circuits were designed for a 6-kA/cm2Nb/AlOx/Nb junction process with 10 mask levels including one ground plane and two Nb wiring layers. The initial design and optimization of the circuit parameters were achieved by means of the optimization functions in a circuit simulator, PSCAN2, to ensure that important circuit parameters, Josephson critical current (IC), bias current (Ibias), and inductance satisfied minimal margin requirements. Critical margins of ICand Ibiaswere then further improved manually. To compensate the scattering in the circuit parameters from fabrication by design as much as possible, the critical junction parameters were optimized to further centralize the IC. The library cells were laid out following our design rules determined by systematic experiments on process control monitors (PCM). Basic cells including Josephson transmission lines, splitters, confluence buffers, D flip-flops, T flip-flops, and XOR and NDRO gates were designed, fabricated, and successfully tested at low frequencies. Wide overlaps of the operating regions for the common bias voltages were confirmed.
Rapid single flux quantum technology is one of the most promising developments for future high-speed microprocessors, network routers, and analog-to-digital converters. This technology is based on well-timed signals and fast signal transmission. However, as the complexity of the circuits or the operating frequency of these signals increase, it becomes harder to achieve a successful timing scheme. Another case that prevents successful timing is thermal noise, which becomes more significant with the increase of the number of cells. Earlier studies on noise analysis show that the timing variations of the delay on a cascaded path vary up to 10% compared with the delay of the same type of single cell. On the other hand, circuit parameters may change during the fabrication process, and as a result, timing of the cell differs from the design value. For these reasons, we define a statistical model for the wiring cells, such as Josephson transmission lines, splitters, and mergers that can be used to calculate the timing delay and jitter instead of time-consuming simulations. We also discuss a possible method to identify the sensitive paths to the delay fluctuations among different alternatives. In this study, we analyze the delay and the jitter of cascaded combinations of the most common wiring cells to determine the correlation effect on delay and jitter between the consecutive gates. Then, we propose a statistical method to analyze these timings faster and easier. Finally, we discussed how to estimate the output probability of the clocked gates without performing an actual simulation.
At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.
Rapid single flux quantum (RSFQ) digital circuits have reached the level of medium- to large-scale of integration. At this level, existing design methodologies, developed specifically for RSFQ circuits, have become computationally inefficient. Applying mature semiconductor methodologies to the design of RSFQ circuits, one encounters substantial difficulties originating from the differences between both technologies. In this paper, a new design methodology aimed at large-scale RSFQ circuits is proposed. This methodology is based on a semiconductor semicustom design approach. An established design methodology for small-stale RSFQ digital circuits, based on circuit (junction-level) simulation and device parameter optimization, is used for the design of basic RSFQ cells. A library composed of about 20 basic RSFQ cells has been developed based on this approach. A novel design methodology for large-scale circuits, presented in this paper, is based on logic (gate-level) simulation and timing optimization. This methodology has been implemented around the Cadence integrated design environment and used successfully at the University of Rochester for the design of two large-scale digital circuits.
The authors consider the design of a binary carry full-adder cell using the logic gates and buffers belonging to the rapid single-flux-quantum (RSFQ) logic family. They have taken advantage of the unique properties of RSFQ pulse logic to realize two designs: one using two logic gates and a toggle flip-flop in two stages of logic, the other using two logic gates in one stage of logic. They have determined the parameter margins of the two full-adder cells and optimized them to obtain critical margins approaching +or-30%. Simulations of the full-adder cells have revealed critical delays and maximum clock frequencies of 58 ps and 17 GHz and 33 ps and 30 GHz, respectively.>