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IEEE Transactions on Applied Superconductivity

A Statistical Approach to Delay, Jitter and Timing of Signals of RSFQ Wiring Cells and Clocked Gates

M. Celik, Ali Bozbey

Published Dec 31, 2012• 18 citations
Publisher

Abstract

Rapid single flux quantum technology is one of the most promising developments for future high-speed microprocessors, network routers, and analog-to-digital converters. This technology is based on well-timed signals and fast signal transmission. However, as the complexity of the circuits or the operating frequency of these signals increase, it becomes harder to achieve a successful timing scheme. Another case that prevents successful timing is thermal noise, which becomes more significant with the increase of the number of cells. Earlier studies on noise analysis show that the timing variations of the delay on a cascaded path vary up to 10% compared with the delay of the same type of single cell. On the other hand, circuit parameters may change during the fabrication process, and as a result, timing of the cell differs from the design value. For these reasons, we define a statistical model for the wiring cells, such as Josephson transmission lines, splitters, and mergers that can be used to calculate the timing delay and jitter instead of time-consuming simulations. We also discuss a possible method to identify the sensitive paths to the delay fluctuations among different alternatives. In this study, we analyze the delay and the jitter of cascaded combinations of the most common wiring cells to determine the correlation effect on delay and jitter between the consecutive gates. Then, we propose a statistical method to analyze these timings faster and easier. Finally, we discussed how to estimate the output probability of the clocked gates without performing an actual simulation.

DOI
10.1109/tasc.2012.2237215

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Rapid single flux quantum technology is one of the most promising developments for future high-speed microprocessors, network routers, and analog-to-digital converters. This technology is based on well-timed signals and fast signal transmission. However, as the complexity of the circuits or the operating frequency of these signals increase, it becomes harder to achieve a successful timing scheme. Another case that prevents successful timing is thermal noise, which becomes more significant with the increase of the number of cells. Earlier studies on noise analysis show that the timing variations of the delay on a cascaded path vary up to 10% compared with the delay of the same type of single cell. On the other hand, circuit parameters may change during the fabrication process, and as a result, timing of the cell differs from the design value. For these reasons, we define a statistical model for the wiring cells, such as Josephson transmission lines, splitters, and mergers that can be used to calculate the timing delay and jitter instead of time-consuming simulations. We also discuss a possible method to identify the sensitive paths to the delay fluctuations among different alternatives. In this study, we analyze the delay and the jitter of cascaded combinations of the most common wiring cells to determine the correlation effect on delay and jitter between the consecutive gates. Then, we propose a statistical method to analyze these timings faster and easier. Finally, we discussed how to estimate the output probability of the clocked gates without performing an actual simulation.
All complex devices in rapid single flux quantum (RSFQ) technique work at much lower clock rates than possible for simple cells. New data driven self timed or asynchronous concepts can reduce this gap, but even in this case still a discrepancy between simulation and experiment is shown. It has been pointed out in previous studies, that the influence of thermal fluctuations in RSFQ circuits is divided into static and dynamic switching bit errors as well as timing jitter induced failures. The bit error rate depends exponentially on the temperature and is not the main issue in the low temperature technique. Our last results show for the first time, that the variance of the switching time is much slower decreased by reducing the temperature and is still important at 4.2 K. We describe a general method for calculating the switching time distribution for RSFQ cells. Furthermore, we present detailed results for a timing analysis of a dc/SFQ-converter. The delay between output signal and the input current ramp shows a variation over 1 ps which is more than 10% of the switching time itself. This new understanding of the background of timing jitter enables a goal-oriented improvement in the design process of RSFQ circuits.
Successful fabrication and demonstration of complex Rapid Single Flux Quantum (RSFQ) circuits depend heavily on the reliability of the cell library that is used for the design. In large-scale RSFQ integrated circuits, delay fluctuations (jitter) of each cell may occur due to fabrication tolerances. The fabrication-induced jitter of each cell might accumulate at each stage and bring out larger variations comparable with the designed delay. If such jitter is not considered while arranging timing of the circuit, it may cause the circuit to malfunction due to the shifting of SFQ pulses. Therefore, it is important to optimize and determine the delay fluctuations of each cell well before designing a large-scale integrated circuit. There are quite a number of parameters that affect the functioning and the performance of a logic gate; hence, an optimization tool is required. In this study, the progress on development of an optimization tool for a digital RSFQ cell library composed of fundamental logic gates, such as Josephson transmission lines, D-flip-flops, T-Flip-flops, splitters, and mergers are presented. Particle swarm optimization is used for an optimization algorithm, which determines the circuit parameters with minimum delay and/or jitter satisfying the required critical margin conditions.
Digital superconducting systems based on Josephson junctions make generally use of the synchronous timing strategy. Today, one of its most promising applications is the high speed and high dynamic range signal sensing. A digital signal acquisition system should have a high resolution as well as a short sampling interval with a well known and constant time period. Short term clock fluctuations (clock jitter) induced by thermal noise can significantly disturb the system operation due to hazards of timing constraint violations. This uncertainty in the time period is currently a strong limitation for further improvements of fast signal sensing systems based on superconductive electronics. Recently, several theoretical and experimental studies describe the timing jitter in simple circuits, like Josephson transmission lines. In the presented work, we analyse different fabrication technologies for rapid single flux quantum (RSFQ) electronics and predict their timing jitter by the numerical solution of stochastic differential equations. We obtained a very good agreement between our simulation data and recent experimental results.
At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.
The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.
In single-flux-quantum (SFQ) circuits, the delay produced by the Josephson transmission line (JTL) is comparable with or larger than the one produced by the logic cells. Therefore, it is difficult to find the routes that satisfy the timing constraints in a large circuit manually. To overcome this obstacle, we propose a two-step automatic JTL routing technology that performs coarse and fine timing adjustments. First, an automatic router draws dummy wires within coarse timing constraints, and then the dummy wires are replaced with JTL cells. Fine timing adjustments are done in the latter step. Some JTL cells in clock and data paths are replaced with faster JTL cells so that clock signals always arrive earlier than data signals at clocked-gates. Two example circuits were designed using the automatic JTL routing technology. One is composed of nearly 600 Josephson junctions. It was experimentally tested up to 35 GHz with on-chip test components. The other is composed of about 4000 Josephson junctions. After the fine timing adjustment, logic simulation showed that it can operate at 20 GHz. We also experimentally confirmed its correct operations at low speed.