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IEEE Transactions on Applied Superconductivity

Bit error rate determination of RSFQ logic cells by means of noise analysis of basic network components

Thomas Ortlepp, Hannes Toepfer, Friedrich Uhlmann

Published Jun 1, 2003• 3 citations
Publisher

Abstract

The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.

DOI
10.1109/tasc.2003.813920

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A major restriction in the development of a working Rapid Single Flux Quantum (RSFQ) logic circuit with high-Tc superconductors is given by the influence of thermal noise. This gives reason to ask for a general determination of the digital bit error rate. As other approaches, our method of calculating the switching probability is based on the Fokker-Planck equation. In the past few years the bit error rates for a single Josephson junction, SQUIDs and the comparator were calculated by using this theory. We demonstrate numerical solution of the multidimensional Fokker-Planck equation to calculate bit error rates due to thermal noise for a Toggle Flip Flop circuit. In the present work, we combine thermal noise analysis with the effects of process variations in order to derive rules for designing high-Tc RSFQ logic circuits.

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The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.

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We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.

IEEE Transactions on Applied Superconductivity•Jun 1, 1999•50 citations
The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.
A major restriction in the development of a working Rapid Single Flux Quantum (RSFQ) logic circuit with high-Tc superconductors is given by the influence of thermal noise. This gives reason to ask for a general determination of the digital bit error rate. As other approaches, our method of calculating the switching probability is based on the Fokker-Planck equation. In the past few years the bit error rates for a single Josephson junction, SQUIDs and the comparator were calculated by using this theory. We demonstrate numerical solution of the multidimensional Fokker-Planck equation to calculate bit error rates due to thermal noise for a Toggle Flip Flop circuit. In the present work, we combine thermal noise analysis with the effects of process variations in order to derive rules for designing high-Tc RSFQ logic circuits.
All complex devices in rapid single flux quantum (RSFQ) technique work at much lower clock rates than possible for simple cells. New data driven self timed or asynchronous concepts can reduce this gap, but even in this case still a discrepancy between simulation and experiment is shown. It has been pointed out in previous studies, that the influence of thermal fluctuations in RSFQ circuits is divided into static and dynamic switching bit errors as well as timing jitter induced failures. The bit error rate depends exponentially on the temperature and is not the main issue in the low temperature technique. Our last results show for the first time, that the variance of the switching time is much slower decreased by reducing the temperature and is still important at 4.2 K. We describe a general method for calculating the switching time distribution for RSFQ cells. Furthermore, we present detailed results for a timing analysis of a dc/SFQ-converter. The delay between output signal and the input current ramp shows a variation over 1 ps which is more than 10% of the switching time itself. This new understanding of the background of timing jitter enables a goal-oriented improvement in the design process of RSFQ circuits.
In the design of electronic applications (for example, rapid single flux quantum (RSFQ) circuits), the properties of Josephson junctions (JJs) provided by technology are the major requirement. The characteristic voltage IcRn an dt he dynamic parameter βc are non-negligibly important, bu tt he external shunted junctions are only completely described by including the parasitic inductance between the junction area and the shunt resistor. The first publications of the RSFQ circuit technique were closely followed by many studies on the dynamic influence of this inductance. It has been pointed out that no practical value of this parameter has to be taken into account in the circuit design and optimization process. The operation of RSFQ logic circuits made of high-temperature superconductors (HTS) are strongly influenced by thermal noise. Our paper contains the determination of the digital bit-error rate for all different types of JJs by using a Fokker–Planck equation for describing the influence of thermal fluctuations. Ou ra nalysis shows that the parasitic inductance cannot be neglected in terms of noise. The intrinsic shunted junctions like high current density-, SINIS- and all kinds of HTS-JJs provide the best noise immunity for a fixed temperature.
Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.
The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.
We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.