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IEEE Transactions on Applied Superconductivity

Noise Induced Timing Jitter: A General Restriction for High Speed RSFQ Devices

Thomas Ortlepp, Friedrich Uhlmann

Published Jun 1, 2005• 21 citations
Publisher

Abstract

All complex devices in rapid single flux quantum (RSFQ) technique work at much lower clock rates than possible for simple cells. New data driven self timed or asynchronous concepts can reduce this gap, but even in this case still a discrepancy between simulation and experiment is shown. It has been pointed out in previous studies, that the influence of thermal fluctuations in RSFQ circuits is divided into static and dynamic switching bit errors as well as timing jitter induced failures. The bit error rate depends exponentially on the temperature and is not the main issue in the low temperature technique. Our last results show for the first time, that the variance of the switching time is much slower decreased by reducing the temperature and is still important at 4.2 K. We describe a general method for calculating the switching time distribution for RSFQ cells. Furthermore, we present detailed results for a timing analysis of a dc/SFQ-converter. The delay between output signal and the input current ramp shows a variation over 1 ps which is more than 10% of the switching time itself. This new understanding of the background of timing jitter enables a goal-oriented improvement in the design process of RSFQ circuits.

DOI
10.1109/tasc.2005.849830

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All complex devices in rapid single flux quantum (RSFQ) technique work at much lower clock rates than possible for simple cells. New data driven self timed or asynchronous concepts can reduce this gap, but even in this case still a discrepancy between simulation and experiment is shown. It has been pointed out in previous studies, that the influence of thermal fluctuations in RSFQ circuits is divided into static and dynamic switching bit errors as well as timing jitter induced failures. The bit error rate depends exponentially on the temperature and is not the main issue in the low temperature technique. Our last results show for the first time, that the variance of the switching time is much slower decreased by reducing the temperature and is still important at 4.2 K. We describe a general method for calculating the switching time distribution for RSFQ cells. Furthermore, we present detailed results for a timing analysis of a dc/SFQ-converter. The delay between output signal and the input current ramp shows a variation over 1 ps which is more than 10% of the switching time itself. This new understanding of the background of timing jitter enables a goal-oriented improvement in the design process of RSFQ circuits.
We have carried out measurements of bit error rate (BER) of Rapid Single-Flux-Quantum (RSFQ) XOR gates with various nominal dc power supply voltages (from 0.1 V to 1.0 mV), operating at speeds up to 25 GHz. (For these gates, implemented using HYPRES' standard, 3.5-/spl mu/m, 10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process, this speed is close to maximum.) A special on-chip RSFQ test circuit allowed high-speed measurements of BER in the range from 10/sup -9/ to 10/sup -13/ to be carried out. As a result of these experiments, a new type of thermal-fluctuation-induced digital errors in RSFQ circuits has been identified. These "timing" errors arise at high speed due to time jitter of data and clock pulses. We have developed a simple theory of these errors which allows a fair description of the experimental data. The theory shows that in some cases the timing errors may be an important factor limiting speed performance of RSFQ circuitry. Nevertheless, our XOR gates could operate at 25 GHz with BER below 10/sup -13/ at the standard temperature (4.2 K) at any dc power supply voltage in our range. For the lowest voltage (0.1 Volt) the calculated static power dissipation in the gate was as low as 23 nanowatts, lower than the unavoidable dynamic dissipation (43 nanowatts).
The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.
Rapid single flux quantum technology is one of the most promising developments for future high-speed microprocessors, network routers, and analog-to-digital converters. This technology is based on well-timed signals and fast signal transmission. However, as the complexity of the circuits or the operating frequency of these signals increase, it becomes harder to achieve a successful timing scheme. Another case that prevents successful timing is thermal noise, which becomes more significant with the increase of the number of cells. Earlier studies on noise analysis show that the timing variations of the delay on a cascaded path vary up to 10% compared with the delay of the same type of single cell. On the other hand, circuit parameters may change during the fabrication process, and as a result, timing of the cell differs from the design value. For these reasons, we define a statistical model for the wiring cells, such as Josephson transmission lines, splitters, and mergers that can be used to calculate the timing delay and jitter instead of time-consuming simulations. We also discuss a possible method to identify the sensitive paths to the delay fluctuations among different alternatives. In this study, we analyze the delay and the jitter of cascaded combinations of the most common wiring cells to determine the correlation effect on delay and jitter between the consecutive gates. Then, we propose a statistical method to analyze these timings faster and easier. Finally, we discussed how to estimate the output probability of the clocked gates without performing an actual simulation.
We have designed and tested a Rapid Single-Flux-Quantum (RSFQ) circuit for experimental measurement of the fluctuation-induced threshold uncertainty of switching of SFQ comparators, which are essential components of RSFQ logic devices, analog-to-digital converters, and digital SQUIDs. Statistical density of the switching events in comparators using externally-overdamped Nb-trilayer Josephson junctions has been found to be in agreement with the distribution which follows from a simple theory based on a time-dependent harmonic-oscillator model of the device. Width of the distribution (i.e, the single-shot current resolution of the comparator) measured as a function of temperature in the range 1.7-4.2 K corresponds to fundamental (thermal/quantum) fluctuations, with no evidence of excess noise sources.>
A major restriction in the development of a working Rapid Single Flux Quantum (RSFQ) logic circuit with high-Tc superconductors is given by the influence of thermal noise. This gives reason to ask for a general determination of the digital bit error rate. As other approaches, our method of calculating the switching probability is based on the Fokker-Planck equation. In the past few years the bit error rates for a single Josephson junction, SQUIDs and the comparator were calculated by using this theory. We demonstrate numerical solution of the multidimensional Fokker-Planck equation to calculate bit error rates due to thermal noise for a Toggle Flip Flop circuit. In the present work, we combine thermal noise analysis with the effects of process variations in order to derive rules for designing high-Tc RSFQ logic circuits.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested