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IEEE Transactions on Applied Superconductivity

Pulse jitter and timing errors in RSFQ circuits

Alexander V. Rylyakov, Konstantin K. Likharev

Published Jun 1, 1999• 69 citations
Publisher

Abstract

We have carried out measurements of bit error rate (BER) of Rapid Single-Flux-Quantum (RSFQ) XOR gates with various nominal dc power supply voltages (from 0.1 V to 1.0 mV), operating at speeds up to 25 GHz. (For these gates, implemented using HYPRES' standard, 3.5-/spl mu/m, 10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process, this speed is close to maximum.) A special on-chip RSFQ test circuit allowed high-speed measurements of BER in the range from 10/sup -9/ to 10/sup -13/ to be carried out. As a result of these experiments, a new type of thermal-fluctuation-induced digital errors in RSFQ circuits has been identified. These "timing" errors arise at high speed due to time jitter of data and clock pulses. We have developed a simple theory of these errors which allows a fair description of the experimental data. The theory shows that in some cases the timing errors may be an important factor limiting speed performance of RSFQ circuitry. Nevertheless, our XOR gates could operate at 25 GHz with BER below 10/sup -13/ at the standard temperature (4.2 K) at any dc power supply voltage in our range. For the lowest voltage (0.1 Volt) the calculated static power dissipation in the gate was as low as 23 nanowatts, lower than the unavoidable dynamic dissipation (43 nanowatts).

DOI
10.1109/77.783794

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We have carried out measurements of bit error rate (BER) of Rapid Single-Flux-Quantum (RSFQ) XOR gates with various nominal dc power supply voltages (from 0.1 V to 1.0 mV), operating at speeds up to 25 GHz. (For these gates, implemented using HYPRES' standard, 3.5-/spl mu/m, 10 /spl mu/A//spl mu/m/sup 2/ Nb-trilayer process, this speed is close to maximum.) A special on-chip RSFQ test circuit allowed high-speed measurements of BER in the range from 10/sup -9/ to 10/sup -13/ to be carried out. As a result of these experiments, a new type of thermal-fluctuation-induced digital errors in RSFQ circuits has been identified. These "timing" errors arise at high speed due to time jitter of data and clock pulses. We have developed a simple theory of these errors which allows a fair description of the experimental data. The theory shows that in some cases the timing errors may be an important factor limiting speed performance of RSFQ circuitry. Nevertheless, our XOR gates could operate at 25 GHz with BER below 10/sup -13/ at the standard temperature (4.2 K) at any dc power supply voltage in our range. For the lowest voltage (0.1 Volt) the calculated static power dissipation in the gate was as low as 23 nanowatts, lower than the unavoidable dynamic dissipation (43 nanowatts).
Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumption. In this paper, we present two original experiments to demonstrate that it's also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17 GHz, latency of 860 ps and BER of 10/sup -19/ for 3.5 /spl mu/m technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 /spl mu/m technology of TRW, Inc. These figures are in good agreement with our simulations.
All complex devices in rapid single flux quantum (RSFQ) technique work at much lower clock rates than possible for simple cells. New data driven self timed or asynchronous concepts can reduce this gap, but even in this case still a discrepancy between simulation and experiment is shown. It has been pointed out in previous studies, that the influence of thermal fluctuations in RSFQ circuits is divided into static and dynamic switching bit errors as well as timing jitter induced failures. The bit error rate depends exponentially on the temperature and is not the main issue in the low temperature technique. Our last results show for the first time, that the variance of the switching time is much slower decreased by reducing the temperature and is still important at 4.2 K. We describe a general method for calculating the switching time distribution for RSFQ cells. Furthermore, we present detailed results for a timing analysis of a dc/SFQ-converter. The delay between output signal and the input current ramp shows a variation over 1 ps which is more than 10% of the switching time itself. This new understanding of the background of timing jitter enables a goal-oriented improvement in the design process of RSFQ circuits.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
Several novel circuits of the rapid single-flux-quantum (RSFQ) family of Josephson-junction digital devices have been designed, fabricated using a 2.5- mu m 1000-A/cm/sup 2/ Nb trilayer technology, and tested at low frequencies. Numerical simulation and measurements have shown that these circuits have considerably wider parameter margins, due to application of several novel design methods. The authors have also carried out an experiment to measure the rate of errors in a simple RSFQ circuit including an inverter, confluence buffer, and Josephson transmission line. Near the middle of the parameter window at 4.2 K, the error probability was definitely lower than 3*10/sup -15/ per logic operation, despite experimentation with rudimentary shielding and filtering.>
At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.
Key digital circuits for signal processing with tens of gigahertz speed and a few microwatts power dissipation have been recently demonstrated using a simple, 2 /spl mu/m linewidth process. These are the fastest digital circuits reported to date. These circuits use novel rapid single flux quantum (RSFQ) technology that takes advantage of the fundamental properties of superconductivity. In this technology, data and clock are picosecond-long quantized voltage pulses corresponding to the transfer of single magnetic flux quanta, /spl Phisub 0/=h/2e=2 mVps. These SFQ pulses are regenerated at each gate and are processed by circuits comprised of overdamped Josephson junctions interconnected via microstrip inductances. The inherent internal memory of all RSFQ gates (primarily flip-flops), combined with high switching speed, makes serial, bit-pipelined circuit design advantageous. This paper presents experiments in RSFQ digital circuits, including an N/spl times/8b serial multiplier, and on-chip test systems based on RSFQ shift registers and on SFQ samplers. They enable test and study of RSFQ circuits at full GHz speed while communicating with semiconductor electronics at low speed.>