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IEEE Transactions on Applied Superconductivity

HTS multilayer technology for optimal bit-error rate RSFQ cells

D. Cassel, Thomas Ortlepp, K. Ilin, G. Pickartz, B. Kuhlmann, Regina Dittmann, Hannes Toepfer, Alexander M. Klushin, M. Siegel, Friedrich Uhlmann

Published Jun 1, 2003• 4 citations
Publisher

Abstract

The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.

DOI
10.1109/tasc.2003.813881

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IEEE Transactions on Applied Superconductivity•Jun 1, 1999•23 citations
The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.
Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.
The influence of thermal noise gives a major restriction in the development of Rapid Single Flux Quantum (RSFQ) logic circuits with high-T/sub c/ superconductors. In the past, we have demonstrated a general way for determining the digital bit error rate and for predicting operation ranges with good noise immunity. The method is based on a single Fokker-Planck equation which includes the full system dynamics. However, the complexity of this equation increases dramatically with the number of Josephson junctions. Our new approach describes a method to divide an RSFQ logic cell into several basic primitives. They can be characterized quickly in terms of switching probability for a lot of different parameters. From these analyses, look-up tables are built-up. We describe how to combine these data in order to achieve the bit-error rate for the whole cell. While saving more than 90% of computation time, the comparison with our previous results for full system analyses shows less than 4% difference. This approach provides for a powerful tool to include the influence of thermal noise into the optimization process of RSFQ logic circuits as well.
The application of high temperature superconductor (HTS) Josephson junctions in digital rapid single flux quantum circuits requires a careful study of the influence of thermal noise on the bit error rate (BER). We have determined experimentally, for the first time, the BER of a HTS rapid single flux quantum circuit. A comparator, formed by two Josephson junctions, was integrated in a Josephson transmission line ring oscillator, allowing us to perform high speed testing of the comparator at GHz frequencies. For fabrication, focused-electron-beam-irradiated junctions have been used because of their small parameter spread and excellent alignment possibilities. A BER of less than 10−11 was obtained at 39 K.
We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.
The Rapid Single Flux Quantum electronics is a superconducting, naturally digital circuit family which is currently close to getting commercially applied.RSFQ is outstanding by its very low switching energy resulting in a very low power consumption which is the reason for a significant influence on thermal noise.For industrial applications a certain noise immunity is required which is still a challenge especially for circuits of higher complexity.In superconducting electronics resistors are the only on-chip noise sources.We analyzed the influence of each individual resistor in a toggle Flip-Flop circuit to the overall bit-error rate.The shunt resistors of comparator structures are the dominant noise sources and bias resistors have almost no influence.We analyzed in detail the types of thermal introduced switching errors of an toggle Flip-Flop which was optimized with respect to the fabrication yield.Simulation studies were accomplished to investigate the influence of circuit parameters on quality and on quantity of switching errors.By identifying and manipulating the parameters with the most significant influence on the noise susceptibility an enhanced noise immunity of the device can be achieved.The goal is to improve the robustness of RSFQ circuits against the influence of thermal noise for an specific topology by changing the circuit parameters of the device.
There is widespread interest in transferring Single Flux Quantum (SFQ) logic from niobium technology to a suitable HTS technology. The higher operating temperature results in increased noise and associated errors. We have developed numerical methods to study noise induced errors and how they depend on circuit parameters. A simple picture holds for all the circuits studied to date. The error probability shows an error function (integrated Gaussian) distribution. The width of the distribution is circuit dependent, but is 1 to 4 times the noise contribution of a single junction, and the noise free (deterministic) margin corresponds to the point where the error probability is 0.5. The distributions are frequently asymmetric, and minimum error rate does not occur for a design centered between the deterministic margins. A stochastic optimizer has been developed that allows us reoptimize circuits for conditions when noise induced margin narrowing is important. We have used this to study the influence of layout induced stray inductance on the feasibility of HTS circuits using the T flip-flop as an example. Stray inductance appears to be as important as junction reproducibility, and significant improvements are needed to allow high operating temperatures.