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Applied Physics Letters

Measurement of the dynamic error rate of a high temperature superconductor rapid single flux quantum comparator

Ben J. Ruck, B. Oelze, Regina Dittmann, A. Engelhardt, Erik Sodtke, W.E. Booij, Mark G. Blamire

Published May 4, 1998• 15 citations
Publisher

Abstract

The application of high temperature superconductor (HTS) Josephson junctions in digital rapid single flux quantum circuits requires a careful study of the influence of thermal noise on the bit error rate (BER). We have determined experimentally, for the first time, the BER of a HTS rapid single flux quantum circuit. A comparator, formed by two Josephson junctions, was integrated in a Josephson transmission line ring oscillator, allowing us to perform high speed testing of the comparator at GHz frequencies. For fabrication, focused-electron-beam-irradiated junctions have been used because of their small parameter spread and excellent alignment possibilities. A BER of less than 10−11 was obtained at 39 K.

DOI
10.1063/1.121351

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IEEE Transactions on Applied Superconductivity•Mar 1, 2001•17 citations
The application of high temperature superconductor (HTS) Josephson junctions in digital rapid single flux quantum circuits requires a careful study of the influence of thermal noise on the bit error rate (BER). We have determined experimentally, for the first time, the BER of a HTS rapid single flux quantum circuit. A comparator, formed by two Josephson junctions, was integrated in a Josephson transmission line ring oscillator, allowing us to perform high speed testing of the comparator at GHz frequencies. For fabrication, focused-electron-beam-irradiated junctions have been used because of their small parameter spread and excellent alignment possibilities. A BER of less than 10−11 was obtained at 39 K.
The determination of bit error rates in single flux quantum logic circuits operating at temperatures well above the temperature of liquid helium is essential since the question of stability against thermal noise arises. We determined experimentally the static and for the first time the dynamic error rate at temperatures of about 40 K with the help of simple test circuits. The static error rate has been investigated using two different circuits with bicrystal junctions in either single-layer or multilayer configuration. In both cases the internal state of a storage loop was observed by a dc-SQUID. A ring oscillator based on a Josephson transmission line allowed us to measure the dynamic error rate of a Josephson comparator at high frequencies. This circuit has been fabricated using junctions by focused-electron-beam irradiation. It is specially suited for the detection of seldom occurring switching errors.
We have designed and simulated a circuit for the experimental determination of the rate of dynamic switching errors in high-temperature superconductor RSFQ circuits. The proposal is that a series-connected pair of Josephson junctions is read out by SFQ pulses circulating in a ring-shaped Josephson transmission line at high frequency. Suitable bias currents determine the switching thresholds of the junction pair. By measuring the voltage across the transmission line, it is proposed that the occurrence of a switching error can be detected. The bit error rate can be determined from the mean time before false switching together with the SFQ circulation frequency. The circuit design allows measurements over a wide temperature range.
Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.
We model the high temperature superconductor (HTS) rapid single flux quantum (RSFQ) toggle (T) flip-flop including process variations and thermal noise. A Monte Carlo method is used to calculate the theoretical yield of the circuit at speeds ranging from 1-83 GHz and for various process parameter spreads. Thermal noise is also included in the simulations and we calculate bit error rates at 1-150 GHz as a function of temperature. Our results demonstrate quantitatively the difference between HTS layouts with and without parasitic inductance. Furthermore, our simulations suggest that using the existing HTS process with a 250 /spl mu/V I/sub c/R/sub n/ product the T flip-flop operating temperature should be below 40 K in order to obtain bit error rates less than 10/sup -6/ at gigahertz speeds.
The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.
We fabricated and tested high-temperature superconducting (HTS) rapid-single-flux-quantum (RSFQ) circuits using interface-engineered Josephson junction (IEJ). The characteristics of high-speed operation were examined by voltage-divider operation based on the toggle-flip-flop circuit. An operation at 155 GHz was obtained at 15 K and the proper functioning of the voltage divider was observed up to 27 K. Temperature dependence of the maximum operation speed was analyzed by circuit simulation with thermal-noise sources. To achieve higher speed operation using a Josephson junction with a higher I/sub c/R/sub n/ product, we also fabricated an RSFQ balanced comparator using IEJ; proper switching characteristics of the circuit was confirmed up to 190 GHz at 30 K. The bias condition dependencies were studied based on the circuit simulations in the relationship of the I/sub c/R/sub n/ product. The results of circuit simulation indicate that a Josephson junction with an I/sub c/R/sub n/ product of more than 0.7 mV is required for high-speed operation (100 GHz) in high-temperature range (30-40 K). We believe that the IEJ is a promising junction candidate for realizing high-speed operation in a high-temperature range.