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IEEE Transactions on Applied Superconductivity

Limitations on HTS single flux quantum logic

J.S. Satchell

Published Jun 1, 1999• 23 citations
Publisher

Abstract

There is widespread interest in transferring Single Flux Quantum (SFQ) logic from niobium technology to a suitable HTS technology. The higher operating temperature results in increased noise and associated errors. We have developed numerical methods to study noise induced errors and how they depend on circuit parameters. A simple picture holds for all the circuits studied to date. The error probability shows an error function (integrated Gaussian) distribution. The width of the distribution is circuit dependent, but is 1 to 4 times the noise contribution of a single junction, and the noise free (deterministic) margin corresponds to the point where the error probability is 0.5. The distributions are frequently asymmetric, and minimum error rate does not occur for a design centered between the deterministic margins. A stochastic optimizer has been developed that allows us reoptimize circuits for conditions when noise induced margin narrowing is important. We have used this to study the influence of layout induced stray inductance on the feasibility of HTS circuits using the T flip-flop as an example. Stray inductance appears to be as important as junction reproducibility, and significant improvements are needed to allow high operating temperatures.

DOI
10.1109/77.783865

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There is widespread interest in transferring Single Flux Quantum (SFQ) logic from niobium technology to a suitable HTS technology. The higher operating temperature results in increased noise and associated errors. We have developed numerical methods to study noise induced errors and how they depend on circuit parameters. A simple picture holds for all the circuits studied to date. The error probability shows an error function (integrated Gaussian) distribution. The width of the distribution is circuit dependent, but is 1 to 4 times the noise contribution of a single junction, and the noise free (deterministic) margin corresponds to the point where the error probability is 0.5. The distributions are frequently asymmetric, and minimum error rate does not occur for a design centered between the deterministic margins. A stochastic optimizer has been developed that allows us reoptimize circuits for conditions when noise induced margin narrowing is important. We have used this to study the influence of layout induced stray inductance on the feasibility of HTS circuits using the T flip-flop as an example. Stray inductance appears to be as important as junction reproducibility, and significant improvements are needed to allow high operating temperatures.
A high-Tcsuperconducting (HTS) single-flux-quantum (SFQ) logic family including an and gate, an or gate, and an inverter was designed. The circuit parameters were optimized for a Josephson junction's critical current density, which may change due to a temperature change or insufficient run-to-run reproducibility of the fabrication process. New circuit design layout rules were implemented to improve Icx uniformity. As a result, all circuits were successfully tested and show at least plusmn40% critical current density operational margins. An effect of the parasitic capacitance formed by a junction electrode and a ground plane on the operating margins of the and gate was investigated by numerical simulation. Test circuits were fabricated using YBa2Cu3O7-deltaramp-edge junction technology and were operated at temperatures higher than 30 K. Bias current margins were also measured, and they found to be close to the simulated ones.
Single flux quantum (SFQ) circuit elements have been designed and fabricated using the YBa 2 Cu 3 O 7-δ ramp-edge junction technology. Logic operations of SFQ circuit elements, such as a toggle flip-flop (T-FF), a set-reset flip-flop (RS-FF), and a 96-junction Josephson transmission line (JTL), were successfully demonstrated, and dc supply current margins were confirmed up to temperatures higher than 30 K. The circuit layout was improved in order to suppress the critical current (I c ) spread that appears during the junction fabrication procedure. By employing the new circuit layout rule, correct operations at temperatures from 27 K to 34 K with dc supply current margins wider than ±7% were confirmed for the T-FF with a single output. Moreover, the maximum operating frequencies of T-FFs were measured to be 360GHz at 4.2K and 210GHz at 41K, which are substantially higher than the values for the circuits with the conventional layout. According to the simulation result, the maximum operating frequency at 40 K was expected to be approximately 50% of the characteristic frequency at a bit error rate (BER) less than 10 -6 .
Toggle-flip-flop (T-FF) is one of the most important high-Tcsuperconducting single-flux quantum (HTS SFQ) circuit components and has been designed and fabricated by using YBa2Cu3O7-deltaramp-edge junction technology. The circuit layout of the T-FF was improved to suppress the junction critical current (Ic) spread in the circuit. Test circuits, which include a T-FF with a single output for evaluating the logic operation and measuring the operating frequency, were fabricated and their operation characteristics were investigated. The T-FF circuit with a single output was successfully operated and finite direct current (dc) supply current margins were obtained at temperatures from 27 to 34 K. Moreover, the maximum operating frequency of the T-FF was estimated to be 360 GHz at 4.2 K and 114 GHz at 41 K. In addition, reduction of dc supply current margins due to thermal noise was also investigated. According to the numerical simulation in which parasitic inductances were taken into account, the narrowest margin in the T-FF circuit wider than plusmn10% was maintained with a bit-error rate (BER) of 10-6up to 40 K
The operation of Rapid-Single-Flux-Quantum logic (RSFQ) circuits is strongly influenced by thermal noise. Especially for higher temperatures the bit-error rate (BER) is a critical issue. A new design concept focused on improved noise immunity has been developed to reach an optimal BER for high-temperature superconductor (HTS) RSFQ cells. For example, we expect for a T-Flip-Flop (TFF) of our cell library a theoretical improvement of the BER of six orders of magnitude at a temperature of 50 K. To verify the new design approach, we have designed basic RSFQ cells using parameter values derived from our multilayer technology. The process with two superconducting YBCO layers is based on substrates with two bicrystal lines. This paper focuses on the multilayer technology to realize the optimal design parameters. One of the most crucial issues is patterning of small structures on a micron scale, especially the small vias. This new patterning process is described in detail.
In the design of electronic applications (for example, rapid single flux quantum (RSFQ) circuits), the properties of Josephson junctions (JJs) provided by technology are the major requirement. The characteristic voltage IcRn an dt he dynamic parameter βc are non-negligibly important, bu tt he external shunted junctions are only completely described by including the parasitic inductance between the junction area and the shunt resistor. The first publications of the RSFQ circuit technique were closely followed by many studies on the dynamic influence of this inductance. It has been pointed out that no practical value of this parameter has to be taken into account in the circuit design and optimization process. The operation of RSFQ logic circuits made of high-temperature superconductors (HTS) are strongly influenced by thermal noise. Our paper contains the determination of the digital bit-error rate for all different types of JJs by using a Fokker–Planck equation for describing the influence of thermal fluctuations. Ou ra nalysis shows that the parasitic inductance cannot be neglected in terms of noise. The intrinsic shunted junctions like high current density-, SINIS- and all kinds of HTS-JJs provide the best noise immunity for a fixed temperature.
The authors report the design, fabrication, and test results of single flux quantum (SFQ) toggle flip flop circuits. These circuits, investigated as building blocks of an HTS counting ADC, feature a directly coupled readout junction stack similar to those used in LTS RSFQ circuits. The directly coupled circuit delivers higher readout voltage, hence potentially higher operating speed than magnetically coupled alternatives. The circuits were fabricated using two multilayer HTS SNS junction integrated circuit technologies (one at Northrop Grumman and the other at TRW) featuring three YBCO depositions. Initial testing demonstrated toggling of a T-flip flop in response to SFQ pulses generated by integrated dc/SFQ converters. The readout voltage is shown to approach 40% of the junction I/sub C/R/sub N/ product, and as high as 100 /spl mu/V at 65K. Test results are compared with predicted fabrication process parameter requirements. To increase margins and tolerance to process parameter variations, improvements to the design have been made using JSpice and MALT.