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IEEE Transactions on Applied Superconductivity

HTS SFQ T-flip flop with directly coupled readout

A. G. Sun, D.J. Durand, James M. Murduck, Sergey V. Rylov, Martin G. Forrester, B. D. Hunt, John Talvacchio

Published Jun 1, 1999• 14 citations
Publisher

Abstract

The authors report the design, fabrication, and test results of single flux quantum (SFQ) toggle flip flop circuits. These circuits, investigated as building blocks of an HTS counting ADC, feature a directly coupled readout junction stack similar to those used in LTS RSFQ circuits. The directly coupled circuit delivers higher readout voltage, hence potentially higher operating speed than magnetically coupled alternatives. The circuits were fabricated using two multilayer HTS SNS junction integrated circuit technologies (one at Northrop Grumman and the other at TRW) featuring three YBCO depositions. Initial testing demonstrated toggling of a T-flip flop in response to SFQ pulses generated by integrated dc/SFQ converters. The readout voltage is shown to approach 40% of the junction I/sub C/R/sub N/ product, and as high as 100 /spl mu/V at 65K. Test results are compared with predicted fabrication process parameter requirements. To increase margins and tolerance to process parameter variations, improvements to the design have been made using JSpice and MALT.

DOI
10.1109/77.783861

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The authors report the design, fabrication, and test results of single flux quantum (SFQ) toggle flip flop circuits. These circuits, investigated as building blocks of an HTS counting ADC, feature a directly coupled readout junction stack similar to those used in LTS RSFQ circuits. The directly coupled circuit delivers higher readout voltage, hence potentially higher operating speed than magnetically coupled alternatives. The circuits were fabricated using two multilayer HTS SNS junction integrated circuit technologies (one at Northrop Grumman and the other at TRW) featuring three YBCO depositions. Initial testing demonstrated toggling of a T-flip flop in response to SFQ pulses generated by integrated dc/SFQ converters. The readout voltage is shown to approach 40% of the junction I/sub C/R/sub N/ product, and as high as 100 /spl mu/V at 65K. Test results are compared with predicted fabrication process parameter requirements. To increase margins and tolerance to process parameter variations, improvements to the design have been made using JSpice and MALT.
We have fabricated and measured high T/sub c/ superconductor single flux quantum 1-bit flux-counting analog-to-digital converters (ADCs). The ADCs were made with a multilayer all-epitaxial process which incorporates 10 edge SNS (superconductor-normal-superconductor) or step-edge grain boundary (SEGB) Josephson junctions with a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// groundplane. The ADC consists of a quantizer connected to a Toggle flip-flop through a buffer-like stage. Direct readout of the flux state of the T flip-flop was made with a Read SQUID inductively coupled through a hole in the groundplane. The circuits were operated at 65 K and low speeds. The SNS circuits outperformed the SEGB circuits because of their higher readout voltages and tighter critical current spreads.
Toggle-flip-flop (T-FF) is one of the most important high-Tcsuperconducting single-flux quantum (HTS SFQ) circuit components and has been designed and fabricated by using YBa2Cu3O7-deltaramp-edge junction technology. The circuit layout of the T-FF was improved to suppress the junction critical current (Ic) spread in the circuit. Test circuits, which include a T-FF with a single output for evaluating the logic operation and measuring the operating frequency, were fabricated and their operation characteristics were investigated. The T-FF circuit with a single output was successfully operated and finite direct current (dc) supply current margins were obtained at temperatures from 27 to 34 K. Moreover, the maximum operating frequency of the T-FF was estimated to be 360 GHz at 4.2 K and 114 GHz at 41 K. In addition, reduction of dc supply current margins due to thermal noise was also investigated. According to the numerical simulation in which parasitic inductances were taken into account, the narrowest margin in the T-FF circuit wider than plusmn10% was maintained with a bit-error rate (BER) of 10-6up to 40 K
We report a developed single-flux-quantum (SFQ) circuit fabrication process for vertically-stacked interface-treated Josephson junctions by using high-temperature superconductor (HTS) and also report the 500 GHz operation of a toggle flip-flop (TFF). As the first trial of the circuit operation, we fabricated TFF circuits, because TFF is used as a benchmark circuit to indicate potential of the circuit operating speed. To develop the circuit fabrication process, we utilized the counter YBCO layer as a wiring layer. We obtained resistively-shunted-junction behavior of single junction fabricated by new process. In addition, we observed current-voltage characteristics at the input port and the output port of the TFF, and confirmed that the input voltage coincided with twice the output voltage up to 1.1 mV at 4.2 K, which corresponds to the correct operation up to 500 GHz. This frequency is the highest value in HTS circuits ever observed, which suggests the high potential of the vertically-stacked JJs for the circuit operation.
We are introducing a new subfamily of rapid single-flux-quantum (RSFQ) digital cells, based on a single B flip-flop template. The template can be considered as an SFQ flip-flop with up to 4 inputs and 6 outputs. Each input SFQ pulse can change the flip-flop's internal state. Each output presents (in the form of SFQ pulses a specific logic function of the initial state of the cell and input signals. Simple connection of various inputs and/or outputs, combined with shortening or opening of certain branches of the template allows one to implement a variety of RSFQ cells with wide margins. Of these various RSFQ cells, we have designed and successfully tested the T1 cell (asynchronous toggle flip-flop with synchronous destructive readout), single-bit full adder, and single-bit stage of an up-down counter. Experimentally measured margins for dc power supply voltage for these circuits were /spl plusmn/24%, /spl plusmn/24%, and /spl plusmn/17%, respectively.>
We has designed, fabricated, and measured a Single flux quantum (SFQ) toggle flip-flop (TFF). The TFF is widely used in superconductive digital electronics circuits. Many digital devices, such as frequency counter, counting ADC and program counter be used TFF Specially, a program counter may be constructed based on TFF We have designed the newly TFF and obtained high bias margins on test. In this work, we used two circuit simulation tools, WRspice and Julia, as circuit optimization tools. We used XIC for a layout tool. Newly designed TFF had minimum bias margins of +/- and maximum bias margins of +/-(enhanced from +/- ). The designed circuits were fabricated by using Nb technology The test results showed that the re-optimized TFF operated correctly on 100kHz and had a very wide bias margins of +/- .
Single flux quantum (SFQ) circuit elements have been designed and fabricated using the YBa 2 Cu 3 O 7-δ ramp-edge junction technology. Logic operations of SFQ circuit elements, such as a toggle flip-flop (T-FF), a set-reset flip-flop (RS-FF), and a 96-junction Josephson transmission line (JTL), were successfully demonstrated, and dc supply current margins were confirmed up to temperatures higher than 30 K. The circuit layout was improved in order to suppress the critical current (I c ) spread that appears during the junction fabrication procedure. By employing the new circuit layout rule, correct operations at temperatures from 27 K to 34 K with dc supply current margins wider than ±7% were confirmed for the T-FF with a single output. Moreover, the maximum operating frequencies of T-FFs were measured to be 360GHz at 4.2K and 210GHz at 41K, which are substantially higher than the values for the circuits with the conventional layout. According to the simulation result, the maximum operating frequency at 40 K was expected to be approximately 50% of the characteristic frequency at a bit error rate (BER) less than 10 -6 .