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IEEE Transactions on Applied Superconductivity

Zero-Static-Power RSFQ Interconnects via Inductively Biased Unshunted JTLs in a Planarized Double-JJ-Layer Nb Process

Mingfan Chen, Xue Zhang, Junrong Zhao, Maoxiang Chen, Lijuan Li, Liliang Ying, Shucheng Yang

Published Mar 23, 2026• 2 citations
Publisher

Abstract

To improve circuit density and minimize static power dissipation in Single Flux Quantum (SFQ) circuits, this work investigates the application of inductively biased, unshunted Josephson transmission lines (JTLs) which achieve zero static power, compared with regular resistively biased JTLs. Both simulation and experiment results confirm that unshunted JTLs can reliably propagate SFQ pulses with a bias current margin larger than 50%. Based on this, a new fabrication process has been developed featuring eight niobium (Nb) layers, including two Nb/Al-AlOx/Nb junction layers, a dedicated bias-inductor layer, and dual DC-power layers. The vertical functional separation allows 2 active layers. The 1stactive layer uses conventional shunted JJs for logic gates, while the 2nduses unshunted JTLs with inductive bias. This configuration eliminates static power in the interconnect network and simplifies thermal management in stacked Rapid SFQ (RSFQ) architectures. A ten-stage unshunted JTL chain and a hybrid half-adder were designed and demonstrated. Measurements show a 66.7% reduction in static power and a 64.7% reduction in area compared with the Chinese Academy of Scienceconventional single-JJ-layer process. These results verify, for the first time, that inductively biased unshunted interconnects can be monolithically integrated with standard RSFQ logic, offering a scalable path toward ultra-dense, lower-power multilayer superconducting circuits.

DOI
10.1109/tasc.2026.3676750

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To improve circuit density and minimize static power dissipation in Single Flux Quantum (SFQ) circuits, this work investigates the application of inductively biased, unshunted Josephson transmission lines (JTLs) which achieve zero static power, compared with regular resistively biased JTLs. Both simulation and experiment results confirm that unshunted JTLs can reliably propagate SFQ pulses with a bias current margin larger than 50%. Based on this, a new fabrication process has been developed featuring eight niobium (Nb) layers, including two Nb/Al-AlOx/Nb junction layers, a dedicated bias-inductor layer, and dual DC-power layers. The vertical functional separation allows 2 active layers. The 1stactive layer uses conventional shunted JJs for logic gates, while the 2nduses unshunted JTLs with inductive bias. This configuration eliminates static power in the interconnect network and simplifies thermal management in stacked Rapid SFQ (RSFQ) architectures. A ten-stage unshunted JTL chain and a hybrid half-adder were designed and demonstrated. Measurements show a 66.7% reduction in static power and a 64.7% reduction in area compared with the Chinese Academy of Scienceconventional single-JJ-layer process. These results verify, for the first time, that inductively biased unshunted interconnects can be monolithically integrated with standard RSFQ logic, offering a scalable path toward ultra-dense, lower-power multilayer superconducting circuits.
We propose an inductance-load-biasing method in order to reduce power consumption of rapid single flux quantum (SFQ) logic circuits. The main idea arises from the fact that a current source can be made of a large inductor accompanied by a large flux. In our proposal, the current source is composed of a large inductor L b , a small resistor R b and a small voltage source V b . Computer simulations of inductance-load-biased Josephson transmission lines (JTLs) show that an SFQ pulse propagates correctly when L b is large enough even if R b is very small. In order to implement the inductance-load-biased JTL, we have made two different layouts: one uses a large bias inductance L b of a typical stripline structure on a ground plane which occupies a rather large area; the other uses L b in the shape of a coplanar stripline, which costs a smaller area.
Abstract We present SIMIT-Nb08, an eight-layer Nb-based fabrication process for double-active-layer single-flux-quantum (SFQ) digital circuits, aimed at overcoming the routing congestion and integration ‘density wall’ of planar SFQ designs. Both Nb/Al–AlO x /Nb JJ layers were designed with the same nominal critical current density of J c = 6 kA cm −2 , and the measured values were 6.15 and 6.26 kA cm −2 for the lower and upper JJ layers, respectively. This architecture incorporates a dual-ground-plane structure to reduce interlayer electromagnetic coupling and shield stray magnetic flux generated by bias lines. A stop-on-metal chemical mechanical polishing module was implemented to provide a controlled dielectric thickness and a planar surface for upper-layer device fabrication. We validate a double-layer SFQ logic cell library with wide DC bias margins on both layers, and demonstrate ultra-high-speed dynamic operation via a toggle flip-flop-based frequency-divider test exceeding 100 GHz. In addition, the process and cross-layer interconnect reliability are demonstrated by functional operation of a cross-layer one-bit full adder and an eight-bit shift register (SR), where the SR exhibits an effective junction-density improvement of ∼4× over typical single-layer implementations. Post-route benchmarking on a 320-cell SR indicates that SIMIT-Nb08 delivers substantial improvements in power, performance, and area, including a 32.2% reduction in area, a 25.0% increase in maximum operating frequency ( f max ), and a 65.3% reduction in estimated power compared with SIMIT-Nb03 (29.9%, 6.3%, and 62.5%, respectively, compared with SIMIT-Nb04), indicating its potential for routing-constrained SFQ digital circuits.
High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under non-ideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes AC-to-DC converters, introducing area and complexity overhead. This work proposes an alternative method for applying AC biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for AC-to-DC converters. This approach also combines resistive DC biasing with inductive AC biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5%. The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.
Abstract Energy-efficient rapid single flux quantum (ERSFQ) circuits suppress the dominant static power dissipation of Rapid SFQ logic by replacing bias resistors with current-limiting bias Josephson junctions (JJs) and inductors. In practice, however, these JJs introduce power dissipation in the DC bias network due to switching events required to correct data-dependent phase imbalances, with dissipation often comparable to that of dynamic power. This paper presents xeSFQ, a new SFQ logic family that integrates alternating SFQ (xSFQ) encoding with ERSFQ biasing. By enforcing a single pulse per line per logical cycle, xeSFQ maintains uniform phase across the circuit, thereby eliminating bias JJ switching during operation and achieving zero bias network power dissipation. Extensive analog simulations and logic synthesis results, from individual gates to ISCAS and EPFL benchmarks, validate this hypothesis and demonstrate the efficiency and scalability advantages of the proposed approach.
The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of ±29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm2technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.
A simple test circuit of the rapid single-flux-quantum (RSFQ) logic family has been implemented in a planarized all-refractory technology using only two superconducting layers and small Nb/AlOx/Nb Josephson junctions (nominally 1.5×1.5 μm2) with critical current density jc≊6 kA/cm2. A special layout design of the integrated circuit (including a SFQ pulse generator, Josephson transmission line, and T flip–flop) was used to reduce 3D inductances resulting from absence of the ground plane. For samples with various junction parameters, the maximum frequency of the SFQ pulse train, which could be divided by 2 by the flip–flop, ranged from 200 to 370 GHz.