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IEEE Transactions on Applied Superconductivity

A 10 GHz digital amplifier in an ultra-small-spread high-J/sub c/ Nb/Al-AlOx/Nb integrated circuit process

Anupama Bhat, Xiaofan Meng, Stephen R. Whiteley, Mark Jeffery, T. Van Duzer

Published Jun 1, 1999• 26 citations
Publisher

Abstract

We describe a Josephson amplifier fabricated in a high-J/sub c/ process, which is operational to speeds of at least 10 GHz, the highest reported for a voltage-state amplifier. The amplifier converts /spl sim/200 /spl mu/V digital signals to /spl sim/5 mV at 10 GHz and could be used as an interface between two superconducting systems. The bit-error-rate of the circuit was /spl sim/5/spl times/10/sup -12/ at 5 GHz, the lowest reported; bit-error-rate measurements at 10 GHz were not possible. A high-J/sub c/ process which was used to fabricate the amplifier was developed at UC Berkeley with extremely low I/sub c/ spreads; at /spl sim/9.4 kA/cm/sup 2/ /spl sigma/ as low as 0.6% was observed. At /spl sim/10 kA/cm/sup 2/, the typical junction linear dimensions are 1.5 /spl sim/ 2 /spl mu/m, sizes for which it is not possible-with available tools-to make reliable vias that are smaller than the junction. We use a nonplanarized junction process, where the via for contact of a wiring layer to a junction can be larger than the junction.

DOI
10.1109/77.783717

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Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium•Nov 23, 2002•1 citation
We describe a Josephson amplifier fabricated in a high-J/sub c/ process, which is operational to speeds of at least 10 GHz, the highest reported for a voltage-state amplifier. The amplifier converts /spl sim/200 /spl mu/V digital signals to /spl sim/5 mV at 10 GHz and could be used as an interface between two superconducting systems. The bit-error-rate of the circuit was /spl sim/5/spl times/10/sup -12/ at 5 GHz, the lowest reported; bit-error-rate measurements at 10 GHz were not possible. A high-J/sub c/ process which was used to fabricate the amplifier was developed at UC Berkeley with extremely low I/sub c/ spreads; at /spl sim/9.4 kA/cm/sup 2/ /spl sigma/ as low as 0.6% was observed. At /spl sim/10 kA/cm/sup 2/, the typical junction linear dimensions are 1.5 /spl sim/ 2 /spl mu/m, sizes for which it is not possible-with available tools-to make reliable vias that are smaller than the junction. We use a nonplanarized junction process, where the via for contact of a wiring layer to a junction can be larger than the junction.
20 kA/cm2{\hbox{kA/cm}}^{2}kA/cm2 Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency
Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA/cm2Nb/AlOx/Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoNxresistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 mum; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of rapid single flux quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of plusmn13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.
For reliable fabrication of Nb/AlO/sub x//Nb Josephson integrated circuits, a combination of anodization and reactive ion etching techniques was used to make various sizes of high-quality Nb/AlO/sub x//Nb Josephson tunnel junctions with J/sub c/ as high as 5000 A/cm/sup 2/ and V/sub m/(2 mV) as large as 60 mV at 4.2 K. A ten-level process on Nb/AlO/sub x//Nb trilayers with J/sub c/ of 1500 A/cm/sup 2/ was used to fabricate a functional 12-b A/D converter. This circuit included 2.7- mu m-diameter junctions defined by anodization and 5- mu m-diameter junctions defined by reactive ion etching using Nb/sub 2/O/sub 5/ and Al as etch stops. A lift-off process with image-reversal photoresist was used to define SiO/sub 2/ insulators, Mo resistors, and Au resistors. Mo resistor values were adjusted by reactive ion etching. Measurements of the completed circuit show that all circuit components had correct values to well within design tolerance.
We proposed and successfully demonstrated a high-speed Josephson IC to semiconductor IC output interface circuit combining a high electron mobility transistor (HEMT) amplifier and Josephson high-voltage drivers successfully. We developed a 0.5-/spl mu/m gate 77-K wide-band analog monolithic HEMT amplifier for the interface. The HEMT device consisted of InGaP/InGaAs materials stable even at 77 K. The amplifier has a differential amplifier as a first stage to cancel out ground-level fluctuations in the Josephson IC and showed a voltage gain of 23 dB and /spl sim/3-dB frequency of 8 GHz. A 0.63-V/sub p-p/ output was obtained from a 5-GHz, 30-mV/sub p-p/ complementary input signal. We succeeded in transfer ring a voltage signal from 10-stack Josephson high-voltage drivers to a 50-/spl Omega/ system at room temperature with 0.7-V/sub p-p/ amplitude at 300-MHz clock using the HEMT amplifier.
A 1-GHz-clock Josephson microcomputer system was developed to demonstrate the possibility of a high-speed superconducting computer system. It consists of a 4-b data processor chip and a 1-kb RAM chip. For the fabrication of these Josephson integrated circuits, a cross-shaped Nb-AlO/sub x/-Nb Josephson junction process was developed in order to realize small junction size and improve critical current uniformity, and has made fabrication of LSIs with several thousand gates possible. A latchup-free DC flip-flop is an important element in the high-speed Josephson logic and memory circuits, having been applied to an all-DC-powered Josephson RAM with asynchronous access capability. A low-inductance chip-to-chip carrier is an architectural and design concept for the Josephson computer's 1-GHz-clock operation, suppressing the crosstalk between the AC power and the output signals. Each chip is 7 mm square and is fabricated using a 2.5- mu m-rule Nb-AlO/sub x/-Nb junction process. The chips are connected on a superconducting carrier by solder bumps in a die size of 15 mm by 25 mm. The system is constructed from 8123 Josephson interferometer devices and is operable in a 1-ns cycle with 50-mW power dissipation.
We report the development of a 256-stage, one-bit superconducting digital correlator functionally tested at a highest clock frequency of 10.232 GHz and data rate of 1.279 Gb/s. The correlator consists of two 256-bit shift registers for delay and storage, 256 exclusive-OR gates for multiplication, and 256 shunted SQUID's to produce an analog summing output. It is fabricated using a Nb/AlO/sub x//Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The 5-mm square chip uses about 4350 Nb/AlO/sub x//Nb Josephson junctions and consumes about 0.4 mW.>
Superconductive electronics offers a unique combination of high bandwidth and low power for mission critical hardware such as digital processors at 20 to 100 GHz, microwatt per bit analog to digital converters, large digital switches at multi-Gb/s data rates, and low noise parametric amplifiers. This cryogenic technology, typically operating at a few degrees or a few tens of degrees Kelvin, depends upon the unique physics of superconducting materials such as Nb, NbN, and YBaCuO, and the fundamental circuit element, the Josephson junction (JJ) to create unique architectures of unprecedented design efficiency and performance. These circuits are based on the single flux quantum (SFQ) logic family, a technology that has no parallel in semiconductor electronics. Digital data is transmitted by voltage pulses with amplitude less than 1 mV, but at extremely high speeds. Individual gates have been operated as high as 370 GHz. In this paper, we present a brief overview of superconductive digital technology, describe some recent circuits, and discuss how the challenges to superconductive technology are being met, including the use of multi-chip module (MCM) technology, and the potential use of III-V HBT and HEMT circuits to provide interface drivers and amplifiers, possibly operated cryogenically.