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IEEE Journal of Solid-State Circuits

A multigigahertz Josephson-semiconductor interface circuit using 77-K differential monolithic HEMT amplifier and 4.2-K JJ high-voltage driver for superconductor-semiconductor electronic hybrid systems

N. Harada, A. Watanabe, Yuji Awano, K. Hikosaka, Naoki Yokoyama

Published Jan 1, 2000• 5 citations
Publisher

Abstract

We proposed and successfully demonstrated a high-speed Josephson IC to semiconductor IC output interface circuit combining a high electron mobility transistor (HEMT) amplifier and Josephson high-voltage drivers successfully. We developed a 0.5-/spl mu/m gate 77-K wide-band analog monolithic HEMT amplifier for the interface. The HEMT device consisted of InGaP/InGaAs materials stable even at 77 K. The amplifier has a differential amplifier as a first stage to cancel out ground-level fluctuations in the Josephson IC and showed a voltage gain of 23 dB and /spl sim/3-dB frequency of 8 GHz. A 0.63-V/sub p-p/ output was obtained from a 5-GHz, 30-mV/sub p-p/ complementary input signal. We succeeded in transfer ring a voltage signal from 10-stack Josephson high-voltage drivers to a 50-/spl Omega/ system at room temperature with 0.7-V/sub p-p/ amplitude at 300-MHz clock using the HEMT amplifier.

DOI
10.1109/4.818921

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An output voltage of 150 mV was obtained with a risetime of less than 200 ps at the driver, which contained 104 junctions and 2 resistors. The driver was also used to drive a D-HEMT (high-electron mobility transistor), and an output voltage of 0.9 V with a risetime of 500 ps was obtained from the HEMT. This experiment suggests that the Josephson driver developed can be used for a Josephson computer or a SQUID (superconducting quantum interference device) system as an interface gate to drive room-temperature electronic devices.>
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There is a great deal of interest in amplifiers with extremely high bandwidth, low noise and low power consumption which interface RSFQ circuits with commercial room temperature electronics or amplifying SFQ pulses. In this special application a hybrid amplifier should interface an RSFQ circuitry with a Josephson junction array quantizer chip (JA-Q) at 4.2 K. The input signal for the amplifier is generated by an RSFQ signal generator and the output signal fed-in to a Josephson array quantizer. A voltage gain of about 10 4 with a pattern frequency of 2 GHz for a good transfer of the SFQ pulses is required. Additionally, the JA-Q requires a high output current at low power consumption of the amplifier at the same time. Various hybrid amplifiers based on commercially available p-HEMT transistors in an embedded microwave design were designed and characterized. For the p-HEMT transistor characterization at cryogenic temperatures the biasing settings according to an optimum between voltage gain A V and low power consumption P V were determined. Thus a power consumption of P V = 2 mW and a voltage gain of about A V = 4 per stage were achieved. For a preamplifier and an amplifier concept a number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers and the combination of the amplifiers and the JA-Q at 4.2 K showed their good performance without any disturbances of the quantized voltage steps.
We describe a Josephson amplifier fabricated in a high-J/sub c/ process, which is operational to speeds of at least 10 GHz, the highest reported for a voltage-state amplifier. The amplifier converts /spl sim/200 /spl mu/V digital signals to /spl sim/5 mV at 10 GHz and could be used as an interface between two superconducting systems. The bit-error-rate of the circuit was /spl sim/5/spl times/10/sup -12/ at 5 GHz, the lowest reported; bit-error-rate measurements at 10 GHz were not possible. A high-J/sub c/ process which was used to fabricate the amplifier was developed at UC Berkeley with extremely low I/sub c/ spreads; at /spl sim/9.4 kA/cm/sup 2/ /spl sigma/ as low as 0.6% was observed. At /spl sim/10 kA/cm/sup 2/, the typical junction linear dimensions are 1.5 /spl sim/ 2 /spl mu/m, sizes for which it is not possible-with available tools-to make reliable vias that are smaller than the junction. We use a nonplanarized junction process, where the via for contact of a wiring layer to a junction can be larger than the junction.
Abstract Conventional interfaces for a Josephson-CMOS hybrid system typically rely on Josephson latching drivers (JLDs) or SQUID (Superconducting Quantum InterferenceDevice) stacks to convert weak signals, which are then connected to additional amplifiers providing outputs of 1.2 V or 1.8 V. JLDs output tens of millivolts but require AC bias and precise clock alignment. SQUID stacks reach frequencies of tens of GHz but output few millivolts voltages and occupy large area. To address these challenges, an interface based on SiGe BiCMOS(Silicon-Germanium Bipolar Complementary Metal-Oxide-Semiconductor) has been designed, fabricated, and tested. Fabricated using the 130 nm SiGe BiCMOS process, the interface converts 200 μV voltage signals to 1.2 V and consumes only 386 μW per channel at 4.2 K. In low-frequency measurement, the hybrid system supports 21-channel signals conversion without requiring additional CMOS amplifiers, simplifying cryogenic system design. Advantages include eliminating the need for AC bias and clock alignment, while drawbacks like limited speed are also discussed. This technology facilitates the practical application of multichannel superconducting computers and other applications that require efficient signal conversion, making it one of the most promising interface solutions for the hybrid system.