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arXiv:2011.03625 · Superconductor Science and Technology

A compact high frequency voltage amplifier for superconductor–semiconductor logic interface

Sasan Razmkhah, Ali Bozbey, Pascal Febvre

Published Jan 22, 2021• 11 citations
arXivHTMLPDF

Abstract

Abstract The many advantages of cryogenically cooled single-flux quantum (SFQ) circuits imply that the high speed and low voltage output signals must be amplified and interfaced with standard electronics. State-of-the-art low-noise and wide-band amplifiers are required to interface with room temperature electronics. One solution is to place preamplifiers at the cryogenic stage, which requires specific semiconductor design and fabrication. However, a more viable and energy-efficient approach is to integrate the pulsed logic circuit output stages with on-chip superconductor preamplifiers. We designed, fabricated, and tested an on-chip compact voltage multiplier integrated with the output stage of SFQ circuits to increase the voltage amplitude of SFQ pulses. The circuit is designed with the same technology as the logic circuit hence its noise level is lower, and it works at higher frequencies compared to complementary metal-oxide semi-conductor amplifiers and due to quantized nature of it there is no added noise. The fabricated circuit has a compact size of 160 µ m × 320 µ m and provides about 10 dB gain with measured 600 µ V output voltage at frequencies up to ∼25 GHz in simulations. By stacking more levels, over 20 dB gain at circuit level is achievable as shown in simulations. Moreover the gain of the superconductor voltage amplifier is quantized and programmable.

DOI
10.1088/1361-6668/abdedb

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Abstract The many advantages of cryogenically cooled single-flux quantum (SFQ) circuits imply that the high speed and low voltage output signals must be amplified and interfaced with standard electronics. State-of-the-art low-noise and wide-band amplifiers are required to interface with room temperature electronics. One solution is to place preamplifiers at the cryogenic stage, which requires specific semiconductor design and fabrication. However, a more viable and energy-efficient approach is to integrate the pulsed logic circuit output stages with on-chip superconductor preamplifiers. We designed, fabricated, and tested an on-chip compact voltage multiplier integrated with the output stage of SFQ circuits to increase the voltage amplitude of SFQ pulses. The circuit is designed with the same technology as the logic circuit hence its noise level is lower, and it works at higher frequencies compared to complementary metal-oxide semi-conductor amplifiers and due to quantized nature of it there is no added noise. The fabricated circuit has a compact size of 160 µ m × 320 µ m and provides about 10 dB gain with measured 600 µ V output voltage at frequencies up to ∼25 GHz in simulations. By stacking more levels, over 20 dB gain at circuit level is achievable as shown in simulations. Moreover the gain of the superconductor voltage amplifier is quantized and programmable.
There is a great deal of interest in amplifiers with extremely high bandwidth, low noise and low power consumption which interface RSFQ circuits with commercial room temperature electronics or amplifying SFQ pulses. In this special application a hybrid amplifier should interface an RSFQ circuitry with a Josephson junction array quantizer chip (JA-Q) at 4.2 K. The input signal for the amplifier is generated by an RSFQ signal generator and the output signal fed-in to a Josephson array quantizer. A voltage gain of about 10 4 with a pattern frequency of 2 GHz for a good transfer of the SFQ pulses is required. Additionally, the JA-Q requires a high output current at low power consumption of the amplifier at the same time. Various hybrid amplifiers based on commercially available p-HEMT transistors in an embedded microwave design were designed and characterized. For the p-HEMT transistor characterization at cryogenic temperatures the biasing settings according to an optimum between voltage gain A V and low power consumption P V were determined. Thus a power consumption of P V = 2 mW and a voltage gain of about A V = 4 per stage were achieved. For a preamplifier and an amplifier concept a number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers and the combination of the amplifiers and the JA-Q at 4.2 K showed their good performance without any disturbances of the quantized voltage steps.
Interface circuits are the key components that enable the hybrid integration of superconductor and semiconductor digital electronics. The design requirements of superconductor-semiconductor interface circuits vary depending on the application, such as high-performance classical computing, superconducting quantum computing, and digital signal processing. In this survey, various interface circuits are categorized based on the working principle and structure. The superconducting output drivers are explored, which are capable of converting and amplifying, e.g., single flux quantum (SFQ) voltage pulses, to voltage levels that semiconductor circuits can process. Several trade-offs between circuit- and system-level design parameters are examined. Accordingly, parameters such as the data rate, output voltage, power dissipation, layout area, thermal/heat load of cryogenic cables, and bit-error rate are considered.
The connection of RSFQ circuits with commercial room temperature electronics and amplifying SFQ pulses with high data rates require cryogenic interface amplifiers. Such amplifiers should provide extremely high bandwidth, low noise and low power consumption at the same time. Various hybrid amplifiers based on commercial p-HEMT transistors in an embedded microwave design were designed and characterized. Towards the p-HEMT transistor characterization at cryogenic temperature the biasing settings according to an optimum between voltage gain and low power consumption were determined. Thus a total power consumption of 2 mW and a voltage gain of 12 dB per single stage were achieved. For a preamplifier and an amplifier concept a multiple number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers, the combination of an amplifier with a RSFQ circuit at 4.2 K showed their good performances without any disturbance of the RSFQ circuit. Due to the losses between the stages a total gain of 25 dB with a four stage amplifier was achieved; pulse rates went up to 3 Gb/s. The total power consumption was in the range of 8 mW. Further increase of data rates will be achieved by improving the matching between RSFQ output stage and amplifier.
Readout and control of qubits are limiting factors in scaling quantum computers. An ideal solution is to integrate energy-efficient cryogenic circuits close to the qubits to perform control and pre-processing tasks. With orders of magnitude lower power consumption and hence lower noise, Single Flux Quantum (SFQ) and Adiabatic Quantum Flux Parametron (AQFP) superconductor logic families can reach ultimate performance at cryogenic temperatures. We have created a superconductor-based on-chip function generator to control qubits. The generated signal is modulated up to tens of GHz based on the external input waveform applied to the superconductor mixer stage. This circuit works at 4.2K. A radiofrequency (RF) matching circuit transmits the signal to the ~mK stage after digital amplification and noise reduction.
A suitable data link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall time and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA/cm/sup 2/ foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of /spl plusmn/21% on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation.
We present an Rapid Single Flux Quantum (RSFQ) based high voltage driver (HVD) developed for the first amplification stage of a hybrid semiconductor-superconductor memory interface for the RSFQ digital signal processor. Implementation of the driver allows to eliminate the impedance mismatch between RSFQ and standard 50 Omega input of semiconductor electronics and increases the signal-to-noise ratio to reach reliable signal transmission with sufficiently low bit error rate. The driver design is based on the serial stack of 8 SQUIDs with specially configured ground-cuts that form a quasi-coplanar line with 50 Omega impedance. The impedance of the driver has been extracted using 3D EM simulators that accurately take into account multilayer structure and capacitance to the ground. The circuit has been designed for the Hypres 4.5 kA/cm2process. The driver was simulated numerically in PSCAN. The driver can produce output signal at 1 Gbit/s speed and 2.4 mV signal level that is enough to be sensed by low-noise amplifier on the further amplification stage.