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IEEE Transactions on Applied Superconductivity

Stacked double-flux-quantum output amplifier

Quentin Herr

Published Jun 1, 2005• 27 citations
Publisher

Abstract

A suitable data link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall time and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA/cm/sup 2/ foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of /spl plusmn/21% on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation.

DOI
10.1109/tasc.2005.849784

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IEEE Transactions on Applied Superconductivity•Sep 1, 2003•3 citations
A suitable data link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall time and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA/cm/sup 2/ foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of /spl plusmn/21% on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation.
A Double-Flux-Quantum (DFQ) amplifier can multiply its input voltage with quantum accuracy using DFQ generation at under-damped Josephson junctions. We conducted research on digital-to-analogue converters that were implemented using DFQ amplifiers for metrological applications. Conventional DFQ amplifiers were usually operated using two flux-biasing lines. In this study, we redesigned the circuit layout to realize operation using a single flux-biasing line. We designed a new layout of a 20-fold DFQ amplifier and fabricated it using a 2.5-kA/cm 2 Nb/AlO x /Nb process. The measurement was performed in liquid He. The Single-Flux-Quantum (SFQ) pulse train was fed using an over-biasing method, and the input-output characteristics are acquired using an oscilloscope. When the magnetic flux bias current I fb1 was not supplied, the maximum input voltage V inmax was 68 μV, which was 4.2 times larger than the value of 17 μV that was observed in our previous study. V inmax was enhanced to 120 μV when we supplied an I fb1 of 1.00 mA.
Precise voltage generation is a unique feature of single-flux-quantum (SFQ) circuits, in addition to their high-speed digital signal processing with low power consumption. We investigated SFQ pulse-frequency modulation D/A converters for metrological applications. In our SFQ-based D/A converters, the maximum output voltage is determined by the maximum SFQ pulse-frequency at the pulse number multiplier, and by the voltage multiplication factor at the voltage multiplier. In this study, we present our new design for a double-flux-quantum amplifier (DFQA) that works as a quantum voltage multiplier. In the new parameter set, we tuned the damping parameters of the Josephson junctions to realize proper propagation of SFQ pulses. A 1000-fold DFQA designed with the new parameter set was fabricated using a 25-μ A/μ m2Nb/AlOx/Nb integration technology. A 1000-fold voltage multiplication was confirmed for the input voltage up to 43 μV, with a corresponding SFQ repetition frequency of 21 GHz. That is, the output voltage reached 43 mV.
Rapid-single-flux-quantum digital-to-analogue converters (RSFQ-DACs) are now under development for ac voltage standard applications. The voltage multiplier (VM), which precisely amplifies the input voltage, is a key component for RSFQ-DACs. Because the amount of bias current for a conventional VM increases in proportion to its multiplication factor, we have been looking for a VM device which is operated on a different principle. In this paper, we report our design of a 1000-fold VM comprising double flux quantum amplifiers (DFQAs) of which the amount of bias current is independent of its multiplication factor. Test circuits were fabricated using a 2.5 kA/cm2 Nb process. We confirm that the experimental results demonstrate the 1000-fold operation up to 13.2 GHz input SFQ pulse repetition frequency.
An integrated circuit including all basic components of the recently suggested Resistive Single Flux Quantum (RSFQ) logic family has been designed, fabricated and tested successfully. The circuit includes a generator of periodic SFQ pulses, four buffer/amplifier stages for splitting, channeling and regeneration of the pulses, a detector/load stage, and universal RSFQ logic gate (here performing the NOT function). The 10μm design rule circuit employs 13 active Nb - Al2O3- Nb Josephson junctions with the critical current density ∼ 0.5 kA/cm2. externally shunted by Mo resistors with R 1 Ohm. The shunting provided critical damping of the junctions (\beta_{c}\lsim 1) and reasonable (\sim 500 \muV) IcR product. The circuit operation has been tested by measurement of dc voltages\bar{V}_{i}across various Josephson junctions as functions of the dc current through the pulse generator. Correct and stable operation of the circuit for the clock frequencies from 0 to ∼30 GHz has been demonstrated.
We evaluate the input–output characteristics of a 1000-fold voltage multiplier designed for single-flux-quantum (SFQ) digital-to-analog converters. The voltage multiplication is based on the double-flux-quantum amplifier (DFQA) that was originally proposed by Herr in 2005. We have designed and fabricated a 999-stage DFQA using a Nb/AlO x /Nb integration technology. In experiments, we have used two methods of feeding the input SFQ pulse train. The one is an overbiasing method, i.e., the input SFQ pulse train is generated at an overbiased input junction. A 1000-fold voltage multiplication with errors less than ±1% has been confirmed for input voltages of up to 27 µV, of which the corresponding Josephson frequency is 13 GHz. In the other method, a dc/SFQ converter is used for feeding the input SFQ pulse train. A 1000-fold voltage multiplication with an error of −0.03% has been obtained for an input frequency of 600 MHz, of which the corresponding Josephson voltage is 1.2 µV. In experiments, errors in measured voltages are likely to limit the accuracy in evaluation of the multiplication factor.
High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.