IEEE Transactions on Applied Superconductivity

256-stage superconducting digital correlator with analog output

Perng-Fei Yuh, E.E. Stebbins

Published Mar 1, 1995• 1 citation

Abstract

We report the development of a 256-stage, one-bit superconducting digital correlator functionally tested at a highest clock frequency of 10.232 GHz and data rate of 1.279 Gb/s. The correlator consists of two 256-bit shift registers for delay and storage, 256 exclusive-OR gates for multiplication, and 256 shunted SQUID's to produce an analog summing output. It is fabricated using a Nb/AlO/sub x//Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The 5-mm square chip uses about 4350 Nb/AlO/sub x//Nb Josephson junctions and consumes about 0.4 mW.>

DOI: 10.1109/77.384562

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