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IEEE Transactions on Applied Superconductivity

An experimental Josephson digital correlator

Perng-Fei Yuh

Published Jan 1, 1992• 5 citations
Publisher

Abstract

A circuit capable of performing correlation of two sets of 16-sample, one-bit digital data has been designed and tested up to a clock frequency of 12 GHz. The correlator consists of two 16-b shift registers for delay and storage elements and an array of 16 exclusive-OR gates for the multiply-and-add function. It is fabricated using an Nb/AlO/sub x//Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/.>

DOI
10.1109/77.160153

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•Jan 1, 1992•0 citations
A circuit capable of performing correlation of two sets of 16-sample, one-bit digital data has been designed and tested up to a clock frequency of 12 GHz. The correlator consists of two 16-b shift registers for delay and storage elements and an array of 16 exclusive-OR gates for the multiply-and-add function. It is fabricated using an Nb/AlO/sub x//Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/.>
We report the development of a 256-stage, one-bit superconducting digital correlator functionally tested at a highest clock frequency of 10.232 GHz and data rate of 1.279 Gb/s. The correlator consists of two 256-bit shift registers for delay and storage, 256 exclusive-OR gates for multiplication, and 256 shunted SQUID's to produce an analog summing output. It is fabricated using a Nb/AlO/sub x//Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The 5-mm square chip uses about 4350 Nb/AlO/sub x//Nb Josephson junctions and consumes about 0.4 mW.>
A review of Josephson shift-register circuits that have been designed, fabricated, or tested is presented with emphasis on work in the 1980s. Operating speed is most important, since it often limits system performance. Older designs used square-wave clocks, but most modern designs use offset sine waves, with either two or three phases. Operating margins and gate bias uniformity are key concerns. The fastest measured Josephson shift register operated at 2.3 GHz, which compares well with a GaAs shift register that consumes 250 times more power. The difficulties of high-speed testing have prevented many Josephson shift registers from being operated at their highest speeds. Computer simulations suggest that 30-GHz operation is possible with current Nb/Al/sub 2/O/sub 3//Nb technology. Junctions with critical current densities near 10 kA/cm/sup 2/ would make 100-GHz shift registers feasible.>
A Josephson SFQ (single flux quantum) shift register circuit operating under a two-phase power was designed and tested. The test cell was fabricated using the Nb/AlO/sub x//Nb junction SNEAP process. The main data latch is DC biased; the data storage is accomplished by the transfer of a single flux quantum in or out of a SQUID (superconducting quantum interference device) superconducting loop. A two-phase sinusoidal clock with offset is used to operate the circuit. Simulations verify that the operating frequency can go beyond 70 GHz, with operating margins exceeding 20%. Preliminary measurements indicate that the circuit operates as intended.>
Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO/sub /x/Nb Josephson-junction process at a critical-current density of 1000 A/cm/sup 2/. The power dissipation per bit is 3 mu W.>
Experimental superconducting shift registers con- sisting of on-chip clock generators, clock regeneration and dis- tribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic / memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed opera- tion of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AIO,/Nb Josephson-junction process at a critical-current density of 1000 A / cm2. The power dissipation per bit is 3 p.W.